PIC16C71 datasheet(95/337 Pages) MICROCHIP

95 / 337 page

DS30234D-page 95

PIC16C6X

11.4

I2C™ Overview

This section provides an overview of the Inter-Inte-

grated Circuit (I2C) bus, with Section 11.5 discussing

the operation of the SSP module in I2C mode.

The I2C bus is a two-wire serial interface developed by

the Philips® Corporation. The original speciﬁcation, or

standard mode, was for data transfers of up to 100

Kbps. The enhanced speciﬁcation (fast mode) is also

supported. This device will communicate with both

standard and fast mode devices if attached to the same

bus. The clock will determine the data rate.

The I2C interface employs a comprehensive protocol to

ensure reliable transmission and reception of data.

When transmitting data, one device is the “master”

which initiates transfer on the bus and generates the

clock signals to permit that transfer, while the other

device(s) acts as the “slave.” All portions of the slave

protocol are implemented in the SSP module’s hard-

ware, except general call support, while portions of the

master protocol need to be addressed in the

PIC16CXX software. Table 11-3 deﬁnes some of the

I2C bus terminology. For additional information on the

I2C interface speciﬁcation, refer to the Philips docu-

ment “

The I2C bus and how to use it.” #939839340011,

which can be obtained from the Philips Corporation.

In the I2C interface protocol each device has an

address. When a master wishes to initiate a data trans-

fer, it ﬁrst transmits the address of the device that it

wishes to “talk” to. All devices “listen” to see if this is

their address. Within this address, a bit speciﬁes if the

master wishes to read-from/write-to the slave device.

The master and slave are always in opposite modes

(transmitter/receiver) of operation during a data trans-

fer. That is they can be thought of as operating in either

of these two relations:

• Master-transmitter and Slave-receiver

• Slave-transmitter and Master-receiver

In both cases the master generates the clock signal.

The output stages of the clock (SCL) and data (SDA)

lines must have an open-drain or open-collector in

order to perform the wired-AND function of the bus.

External pull-up resistors are used to ensure a high

level when no device is pulling the line down. The num-

ber of devices that may be attached to the I2C bus is

limited only by the maximum bus loading speciﬁcation

of 400 pF.

11.4.1

INITIATING AND TERMINATING DATA

TRANSFER

During times of no data transfer (idle time), both the

clock line (SCL) and the data line (SDA) are pulled high

through the external pull-up resistors. The START and

STOP conditions determine the start and stop of data

transmission. The START condition is deﬁned as a high

to low transition of the SDA when the SCL is high. The

STOP condition is deﬁned as a low to high transition of

the SDA when the SCL is high. Figure 11-14 shows the

START and STOP conditions. The master generates

these conditions for starting and terminating data trans-

fer. Due to the deﬁnition of the START and STOP con-

ditions, when data is being transmitted, the SDA line

can only change state when the SCL line is low.

FIGURE 11-14: START AND STOP

CONDITIONS

SDA

SCL

Start

Condition

Change

of Data

Allowed

Change

of Data

Allowed

Stop

Condition

TABLE 11-3:

I2C BUS TERMINOLOGY

Term

Description

Transmitter

The device that sends the data to the bus.

Receiver

The device that receives the data from the bus.

Master

The device which initiates the transfer, generates the clock and terminates the transfer.

Slave

The device addressed by a master.

Multi-master

More than one master device in a system. These masters can attempt to control the bus at the

same time without corrupting the message.

Arbitration

Procedure that ensures that only one of the master devices will control the bus. This ensure that

the transfer data does not get corrupted.

Synchronization

Procedure where the clock signals of two or more devices are synchronized.

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

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