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ATtiny167-ESSZ датащи(PDF) 279 Page - ATMEL Corporation |
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ATtiny167-ESSZ датащи(HTML) 279 Page - ATMEL Corporation |
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279 / 282 page ![]() 279 7728D–AVR–07/09 ATtiny87/ATtiny167 The time-out counter is disabled during the RESPONSE when this workaround is set. 2. Gain control of the crystal oscillator. The crystal oscillator (0.4 -> 16 MHz) doesn’t latch its gain control (CKSEL/CSEL[2..0] bits): a. The ‘Recover System Clock Source’ command doesn’t returns CSEL[2..0] bits. b. The gain control can be modified on the fly if CLKSELR changes. Problem fix / workaround . a. No workaround. b. As soon as possible, after any CLKSELR modification, re-write the appropriate crystal oscillator setting (CSEL[3]=1 and CSEL[2..0] / CSUT[1..0] bits) in CLKSELR. Code example: ; Select crystal oscillator ( 16MHz crystal, fast rising power) ldi temp1,((0x0F<<CSEL0)|(0x02<<CSUT0)) sts CLKSELR, temp1 ; Enable clock source (crystal oscillator) ldi temp2,(1<<CLKCCE) ldi temp3,(0x02<<CLKC0) ; CSEL = "0010" sts CLKCSR,temp2 ; Enable CLKCSR register access sts CLKCSR,temp3 ; Enable crystal oscillator clock ; Clock source switch ldi temp3,(0x04<<CLKC0) ; CSEL = "0100" sts CLKCSR,temp2 ; Enable CLKCSR register access sts CLKCSR,temp3 ; Clock source switch ; Select watchdog clock ( 128KHz, fast rising power) ldi temp3,((0x03<<CSEL0)|(0x02<<CSUT0)) sts CLKSELR, temp3 ; (*) ; (*) !!! Loose gain control of crystal oscillator !!! ; ==> WORKAROUND ... sts CLKSELR, temp1 ; ... 3. ‘Disable Clock Source’ command remains enabled. In the Dynamic Clock Switch module, the ‘Disable Clock Source’ command remains run- ning after disabling the targeted clock source (the clock source is set in the CLKSELR register). Problem fix / workaround. After a ‘Disable Clock Source’ command, reset the CLKCSR register writing 0x80. Code example: ; Select crystal oscillator ldi temp1,(0x0F<<CSEL0) sts CLKSELR, temp1 ; Disable clock source (crystal oscillator) ldi temp2,(1<<CLKCCE) ldi temp3,(0x01<<CLKC0) ; CSEL = "0001" sts CLKCSR,temp2 ; Enable CLKCSR register access |
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