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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATtiny167-ESSZ датащи(PDF) 170 Page - ATMEL Corporation |
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ATtiny167-ESSZ датащи(HTML) 170 Page - ATMEL Corporation |
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170 / 282 page  170 7728D–AVR–07/09 ATtiny87/ATtiny167 15.5 LIN / UART Description 15.5.1 Reset The AVR core reset logic signal also resets the LIN/UART controller. Another form of reset exists, a software reset controlled by LSWRES bit in LINCR register. This self-reset bit per- forms a partial reset as shown in Table 15-2. 15.5.2 Clock The I/O clock signal (clk i/o) also clocks the LIN/UART controller. It is its unique clock. 15.5.3 LIN Protocol Selection LIN13 bit in LINCR register is used to select the LIN protocol: • LIN13 = 0 (default): LIN 2.1 protocol, • LIN13 = 1: LIN 1.3 protocol. The controller checks the LIN13 bit in computing the checksum (enhanced checksum in LIN2.1 / classic checksum in LIN 1.3). This bit is irrelevant for UART commands. Table 15-2. Reset of LIN/UART Registers Register Name Reset Value LSWRES Value Comment LIN Control Reg. LINCR 0000 0000 b 0000 0000 b x=unknown u=unchanged LIN Status & Interrupt Reg. LINSIR 0000 0000 b 0000 0000 b LIN Enable Interrupt Reg. LINENIR 0000 0000 b xxxx 0000 b LIN Error Reg. LINERR 0000 0000 b 0000 0000 b LIN Bit Timing Reg. LINBTR 0010 0000 b 0010 0000 b LIN Baud Rate Reg. Low LINBRRL 0000 0000 b uuuu uuuu b LIN Baud Rate Reg. High LINBRRH 0000 0000 b xxxx uuuu b LIN Data Length Reg. LINDLR 0000 0000 b 0000 0000 b LIN Identifier Reg. LINIDR 1000 0000 b 1000 0000 b LIN Data Buffer Selection LINSEL 0000 0000 b xxxx 0000 b LIN Data LINDAT 0000 0000 b 0000 0000 b |
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