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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATtiny167-ESSZ датащи(PDF) 138 Page - ATMEL Corporation |
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ATtiny167-ESSZ датащи(HTML) 138 Page - ATMEL Corporation |
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138 / 282 page  138 7728D–AVR–07/09 ATtiny87/ATtiny167 12.11.8 Input Capture Register – ICR1H and ICR1L The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 112. 12.11.9 Timer/Counter1 Interrupt Mask Register – TIMSK1 • Bit 7..6 – Reserved Bits These bits are reserved for future use. • Bit 5 – ICIE1: Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (See ”Interrupt Vectors in ATtiny87/167” on page 59.) is executed when the ICF1 flag, located in TIFR1, is set. • Bit 4..3 – Reserved Bits These bits are reserved for future use. • Bit 2 – OCIE1B: Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The correspond- ing Interrupt Vector (See ”Interrupt Vectors in ATtiny87/167” on page 59.) is executed when the OCF1B flag, located in TIFR1, is set. • Bit 1 – OCIE1A: Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The correspond- ing Interrupt Vector (See ”Interrupt Vectors in ATtiny87/167” on page 59.) is executed when the OCF1A flag, located in TIFR1, is set. • Bit 0 – TOIE1: Timer/Counter Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vec- tor (See ”Interrupt Vectors in ATtiny87/167” on page 59.) is executed when the TOV1 flag, located in TIFR1, is set. Bit 7 6543 210 ICR1[15:8] ICR1H ICR1[7:0] ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0000 000 Bit 7 6543 2 1 0 – – ICIE1 – – OCIE1B OCIE1A TOIE1 TIMSK1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0000 0 0 0 |
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