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ATtiny167-ESSZ датащи(PDF) 121 Page - ATMEL Corporation |
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ATtiny167-ESSZ датащи(HTML) 121 Page - ATMEL Corporation |
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121 / 282 page ![]() 121 7728D–AVR–07/09 ATtiny87/ATtiny167 Figure 12-6 shows a simplified schematic of the logic affected by the COM1A/B1:0 and OCnxi bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM1A/B1:0 and OCnxi bits are shown. When referring to the OC1A/B state, the reference is for the internal OC1A/B Register, not the OC1A/Bi pin. If a system reset occur, the OC1A/B Register is reset to “0”. Figure 12-5. Compare Match Output 19 PB1 / OC1BU DDB1 PINB1 1 0 PORTB1 OC1BU( *) (*) OC1xi: TCCR1D register bit 17 PB3 / OC1BV DDB3 1 0 PORTB3 COM1B0 COM1B1 OC1BV( *) 13 PB5 / OC1BW DDB5 1 0 PORTB5 COM1A0 COM1A1 OCF1A OC1BW( *) PINB3 PINB5 11 PB7 / OC1BX DDB7 1 0 PORTB7 OC1BX( *) PINB7 Waveform Generation Waveform Generation WGM13 FOC1B Top Bottom FOC1A WGM12 WGM11 WGM10 12 PB6 / OC1AX DDB6 1 0 PORTB6 OC1AX( *) PINB6 14 PB4 / OC1AW DDB4 1 0 PORTB4 OC1AW( *) PINB4 18 PB2 / OC1AV DDB2 1 0 PORTB2 OC1AV( *) PINB2 20 PB0 / OC1AU DDB0 1 0 PORTB0 OC1AU( *) PINB0 Count Clear TCNT1 16-bit Counter = Direction OCR1A 16-bit Register = OCR1B 16-bit Register OCF1B |
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