ATtiny167-ESSZ datasheet(116/282 Pages) ATMEL

116 / 282 page

116

7728D–AVR–07/09

ATtiny87/ATtiny167

12.5

Counter Unit

The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter

unit. Figure 12-2 shows a block diagram of the counter and its surroundings.

Figure 12-2. Counter Unit Block Diagram

Signal description (internal signals):

Count

Increment or decrement TCNT1 by 1.

Direction

Select between increment and decrement.

Clear

Clear TCNT1 (set all bits to zero).

clk

Timer/Counter clock.

TOP

Signalize that TCNT1 has reached maximum value.

BOTTOM

Signalize that TCNT1 has reached minimum value (zero).

The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H)

containing the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower

eight bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU

does an access to the TCNT1H I/O location, the CPU accesses the high byte temporary regis-

ter (TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is

read, and TCNT1H is updated with the temporary register value when TCNT1L is written. This

allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the

8-bit data bus. It is important to notice that there are special cases of writing to the TCNT1

are described in the sections where they are of importance.

Depending on the mode of operation used, the counter is cleared, incremented, or decre-

mented at each timer clock (clk

T1). The clkT1 can be generated from an external or internal

clock source, selected by the Clock Select bits (CS12:0). When no clock source is selected

(CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be accessed by the CPU,

independent of whether clk

T1 is present or not. A CPU write overrides (has priority over) all

counter clear or count operations.

The counting sequence is determined by the setting of the Waveform Generation mode bits

(WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B).

There are close connections between how the counter behaves (counts) and how waveforms

are generated on the Output Compare outputs OC1A/B. For more details about advanced

counting sequences and waveform generation, see “Modes of Operation” on page 122.

TEMP (8-bit)

DATA BUS (8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit)

TCNTnL (8-bit)

Control Logic

Count

Clear

Direction

TOVn

(Int.Req.)

Clock Select

TOP

BOTTOM

Edge

Detector

( From Prescaler )

clk

ATtiny167-ESSZ датащи(PDF) 116 Page - ATMEL Corporation

ATtiny167-ESSZ датащи(HTML) 116 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL