ATtiny167-ESSZ datasheet(110/282 Pages) ATMEL

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7728D–AVR–07/09

ATtiny87/ATtiny167

12. 16-bit Timer/Counter1

The 16-bit Timer/Counter unit allows accurate program execution timing (event management),

wave generation, and signal timing measurement. The main features are:

12.1

Features

• True 16-bit Design (i.e., Allows 16-bit PWM)

• Two independent Output Compare Units

• Four Controlled Output Pins per Output Compare Unit

• Double Buffered Output Compare Registers

• One Input Capture Unit

• Input Capture Noise Canceler

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse Width Modulator (PWM)

• Variable PWM Period

• Frequency Generator

• External Event Counter

• Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)

12.2

Overview

Many register and bit references in this section are written in general form.

• A lower case “n” replaces the Timer/Counter number, in this case 1. However, when using

the register or bit defines in a program, the precise form must be used, i.e., TCNT1 for

accessing Timer/Counter1 counter value and so on.

• A lower case “x” replaces the Output Compare unit channel, in this case A or B. However,

when using the register or bit defines in a program, the precise form must be used, i.e.,

OCR1A for accessing Timer/Counter1 output compare channel A value and so on.

• A lower case “i” replaces the index of the Output Compare output pin, in this case U, V, W

or X. However, when using the register or bit defines in a program, the precise form must

be used.

A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 12-1. For the actual

placement of I/O pins, refer to “Pin Configuration” on page 5. CPU accessible I/O Registers,

including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit

locations are listed in the “16-bit Timer/Counter Register Description” on page 132.

ATtiny167-ESSZ датащи(PDF) 110 Page - ATMEL Corporation