MPC8610EC datasheet(19/96 Pages) FREESCALE

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Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8610.

Figure 2. Overshoot/Undershoot Voltage for M/B/OVIN

The MPC8610 core voltage must always be provided at nominal VDD_Core (see Table 3 for actual recommended core voltage).

Voltage to the external interface I/Os are provided through separate sets of supply pins and must be provided at the voltages

shown in Table 3. The input voltage threshold scales with respect to the associated I/O supply voltage. OVDD-based receivers

are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a

single-ended differential receiver referenced to each externally supplied MVREF signal (nominally set to GVDD/2) as is

appropriate for the (SSTL-18 and SSTL-2) electrical signaling standards.

2.1.3

Output Driver Characteristics

Table 4 provides information on the characteristics of the output driver strengths. The values are preliminary estimates.

Table 4. Output Drive Capability

Driver Type

Programmable

Output Impedance

(

Ω)

Supply

Voltage

Notes

DDR signals

36 (half strength mode)

GVDD = 2.5 V

1, 4, 6

DDR2 signals

36 (half strength mode)

GVDD = 1.8 V

1, 5, 6

GND

GND – 0.3 V

GND – 0.7 V

Not to Exceed 10%

G/O/B/X/SVDD + 20%

G/O/B/X/SVDD

G/O/B/X/SVDD + 5%

of tCLK

1. tCLK references clocks for various functional blocks as follows:

VIH

VIL

Note:

For DDR, tCLK references MCK.

For LBIU, tCLK references LCLK.

For PCI, tCLK references PCI_CLK or SYSCLK.

For I2C and JTAG, tCLK references SYSCLK.

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