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MPC8610EC датащи(PDF) 61 Page - Freescale Semiconductor, Inc |
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MPC8610EC датащи(HTML) 61 Page - Freescale Semiconductor, Inc |
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61 / 96 page ![]() Electrical Characteristics MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 61 Table 47 describes some AC parameters common to PCI Express protocols. Figure 38. Differential Measurement Points for Rise and Fall Time Figure 39. Single-Ended Measurement Points for Rise and Fall Time Matching Table 47. SerDes Reference Clock Common AC Parameters At recommended operating conditions with X1VDD or X2VDD = 1.0 V ± 5% and 1.025 V ± 5%. Parameter Symbol Min Max Unit Notes Rising Edge Rate Rise Edge Rate 1.0 4.0 V/ns 2, 3 Falling Edge Rate Fall Edge Rate 1.0 4.0 V/ns 2, 3 Differential Input High Voltage VIH +200 mV 2 Differential Input Low Voltage VIL — –200 mV 2 Rising edge rate (SD n_REF_CLK) to falling edge rate (SD n_REF_CLK) matching Rise-Fall Matching —20 % 1, 4 Notes: 1. Measurement taken from single ended waveform. 2. Measurement taken from differential waveform. 3. Measured from –200 to +200 mV on the differential waveform (derived from SD n_REF_CLK minus SDn_REF_CLK). The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered on the differential zero crossing. See Figure 38. 4. Matching applies to rising edge rate for SD n_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a 200 mV window centered on the median cross point where SD n_REF_CLK rising meets SDn_REF_CLK falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The rise edge rate of SD n_REF_CLK should be compared to the fall edge rate of SDn_REF_CLK, the maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 39. VIH = +200 mV VIL = -200 mV 0.0 V SD n_REF_CLK minus SD n_REF_CLK SD n_REF_CLK SD n_REF_CLK SD n_REF_CLK SD n_REF_CLK |
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