MPC8610EC datasheet(25/96 Pages) FREESCALE

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Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

SDn_REF_CLK and SDn_REF_CLK was designed to work with a spread spectrum clock (+0 to 0.5% spreading at 30–33 kHz

rate is allowed), assuming both ends have same reference clock. For better results use a source without significant unintended

modulation.

2.4.2

Real Time Clock Timing

The RTC input is sampled by the platform clock. The output of the sampling latch is then used as an input to the counters of the

PIC. There is no jitter specification. The minimum pulse width of the RTC signal should be greater than 2

× the period of the

platform clock. That is, minimum clock high time is 2

× tMPX, and minimum clock low time is 2 × tMPX. There is no minimum

RTC frequency; RTC may be grounded if not needed.

2.4.3

PCI/PCI-X Reference Clock Timing

When the PCI/PCI-X controller is configured for asynchronous operation, the reference clock for the PCI/PCI-X controller is

not the SYSCLK input, but instead the PCIn_CLK. Table 11provides the PCI/PCI-X reference clock AC timing specifications

for the MPC8610.

2.4.4

Platform Frequency Requirements for PCI-Express and Serial

RapidIO

The MPX platform clock frequency must be considered for proper operation of the high-speed PCI Express and Serial RapidIO

interfaces as described below.

For proper PCI Express operation, the MPX clock frequency must be greater than or equal to:

527 MHz x (PCI-Express link width)

16 / (1 + cfg_net2_div)

Note that at MPX = 333 - 400 MHz, cfg_net2_div = 0 and at MPX > 400 MHz, cfg_net2_div = 1. Therefore, when operating

PCI Express in x8 link width, the MPX platform frequency must be 333-400 MHz with cfg_net2_div = 0 or greater than or

equal to 527 MHz with cfg_net2_div = 1.

For proper Serial RapidIO operation, the MPX clock frequency must be greater than:

2 × (0.80) × (Serial RapidIO interface frequency) × (Serial RapidIO link width)

Table 11. PCI

n_CLK AC Timing Specifications

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Notes

PCI

n_CLK frequency

fPCICLK

—

133

MHz

—

PCI

n_CLK cycle time

tPCICLK

7.5

—

PCI

n_CLK rise and fall time

tPCIKH, tPCIKL

0.6

1.0

2.1

1, 2

PCI

n_CLK duty cycle

tPCIKHKL/tPCICLK

—

Notes:

1. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V.

2. Timing is guaranteed by design and characterization.

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