MPC8610EC datasheet(76/96 Pages) FREESCALE

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MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0

Hardware Design Considerations

Freescale Semiconductor

3.2

Power Supply Design and Sequencing

3.2.1

PLL Power Supply Filtering

Each of the PLLs listed above is provided with power through independent power supply pins (AVDD_Plat, AVDD_Core,

AVDD_PCI, and SDnAVDD, respectively). The AVDD level should always be equivalent to VDD, and preferably these voltages

will be derived directly from VDD through a low frequency filter scheme such as the following.

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide independent

filter circuits per PLL power supply, one to each of the AVDD type pins. By providing independent filters to each PLL the

opportunity to cause noise injection from one PLL to the other is reduced.

This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built

with surface mount capacitors with minimum effective series inductance (ESL). Consistent with the recommendations of

Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small

capacitors of equal value are recommended over a single large value capacitor.

Each circuit should be placed as close as possible to the specific AVDD type pin being supplied to minimize noise coupled from

nearby circuits. It should be possible to route directly from the capacitors to the AVDD type pin, which is on the periphery of

783 FC-PBGA the footprint, without the inductance of vias.

Figure 48 shows the filter circuit for the platform PLL power supplies (AVDD_PLAT).

Figure 48. MPC8610 PLL Power Supply Filter Circuit (for Platform)

Figure 49 shows the filter circuit for the core PLL power supply (AVDD_Core).

Figure 49. MPC8610 PLL Power Supply Filter Circuit (for Core)

The SDnAVDD signals provide power for the analog portions of the SerDes PLLs. To ensure stability of the internal clock, the

power supplied to the PLL is filtered using a circuit similar to the one shown in Figure 50. For maximum effectiveness, the filter

circuit is placed as closely as possible to the SDnAVDD balls to ensure it filters out as much noise as possible. The ground

connection should be near the SDnAVDD balls. The 0.003-µF capacitor is closest to the balls, followed by the two 2.2-µF

capacitors, and finally the 1 ohm resistor to the board supply plane. The capacitors are connected from SDnAVDD to the ground

plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be kept short, wide and

direct.

Figure 50. SerDes PLL Power Supply Filter

2.2 µF

GND

Low ESL Surface Mount Capacitors

AVDD_Plat

VDD_PLAT

VDD_Core

AVDD_Core

2.2 µF

GND

Low ESL Surface Mount Capacitors

2.2 µF 1

0.003 µF

GND

1.0

nAVDD

1. An 0805 sized capacitor is recommended for system initial bring-up.

SVDD

2.2 µF 1

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