MPC8610EC datasheet(57/96 Pages) FREESCALE

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Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

2.17.2.2

DC Level Requirement for SerDes Reference Clocks

The DC level requirement for the MPC8610 SerDes reference clock inputs is different depending on the signaling mode used

to connect the clock driver chip and SerDes reference clock inputs as described below.

•

Differential mode

— The input amplitude of the differential clock must be between 400 and 1600 mV differential peak-peak (or

between 200 and 800 mV differential peak). In other words, each signal wire of the differential pair must have a

single-ended swing less than 800 mV and greater than 200 mV. This requirement is the same for both external DC-

or AC-coupled connection.

— For external DC-coupled connection, as described in Section 2.17.2.1, “SerDes Reference Clock Receiver

Characteristics,” the maximum average current requirements sets the requirement for average voltage (common

mode voltage) to be between 100 and 400 mV. Figure 31 shows the SerDes reference clock input requirement for

DC-coupled connection scheme.

— For external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Since

the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver

operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has

its common mode voltage set to SGND. Each signal wire of the differential inputs is allowed to swing below and

above the command mode voltage (SGND). Figure 32 shows the SerDes reference clock input requirement for

AC-coupled connection scheme.

•

Single-ended mode

— The reference clock can also be single-ended. The SDn_REF_CLK input amplitude (single-ended swing) must be

between 400 and 800 mV peak-peak (from Vmin to Vmax) with SDn_REF_CLK either left unconnected or tied to

ground.

—The SDn_REF_CLK input average voltage must be between 200 and 400 mV. Figure 33 shows the SerDes

reference clock input requirement for single-ended signaling mode.

— To meet the input amplitude requirement, the reference clock inputs might need to be DC- or AC-coupled

externally. For the best noise performance, the reference of the clock could be DC- or AC-coupled into the unused

phase (SDn_REF_CLK) through the same source impedance as the clock input (SDn_REF_CLK) in use.

Figure 31. Differential Reference Clock Input DC Requirements (External DC-Coupled)

Figure 32. Differential Reference Clock Input DC Requirements (External AC-Coupled)

n_REF_CLK

Vmax < 800 mV

Vmin > 0V

100 mV < Vcm < 400 mV

200 mV < Input Amplitude or Differential Peak < 800 mV

n_REF_CLK

Vcm

200mV < Input Amplitude or Differential Peak < 800 mV

Vmax < Vcm + 400 mV

Vmin > Vcm – 400 mV

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