MPC8610EC datasheet(24/96 Pages) FREESCALE

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MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0

Electrical Characteristics

Freescale Semiconductor

2.4.1

System Clock Timing

Table 9 provides the system clock (SYSCLK) AC timing specifications for the MPC8610.

2.4.1.1

SYSCLK and Spread Spectrum Sources

Spread spectrum clock sources are a popular way to control electromagnetic interference emissions (EMI) by spreading the

emitted noise over a wider spectrum and reducing the peak noise magnitude. These clock sources intentionally add long-term

jitter in order to diffuse the EMI spectral content. The jitter specification given in Table 9 considers short-term (cycle-to-cycle)

jitter only and the clock generator’s cycle-to-cycle output jitter should meet the MPC8610 input cycle-to-cycle jitter

requirement. Frequency modulation and spread are separate concerns, and the MPC8610 is compatible with spread spectrum

sources if the recommendations listed in Table 10 are observed.

It is imperative to note that the processor’s minimum and maximum SYSCLK, core, and VCO frequencies must not be exceeded

regardless of the type of clock source. Therefore, systems in which the processor is operated at its maximum rated e600 core

frequency should avoid violating the stated limits by using down-spreading only.

Table 9. SYSCLK AC Timing Specifications

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

SYSCLK frequency

fSYSCLK

—

133

MHz

SYSCLK cycle time

tSYSCLK

7.5

—

SYSCLK rise and fall time

tKH, tKL

0.6

1.0

1.2

SYSCLK duty cycle

tKHK/tSYSCLK

—

SYSCLK jitter

—

±150

4, 5

Notes:

All specifications at recommended operating conditions (see Table 3) with OVDD = 3.3 V ± 165 mV.

1. Caution: The platform to SYSCLK clock ratio and e600 core to platform clock ratio settings must be chosen such that the

resulting SYSCLK, platform, and e600 (core) frequencies do not exceed their respective maximum or minimum operating

frequencies. Refer to Section 3.1.2, “Platform/MPX to SYSCLK PLL Ratio” and Section 3.1.3, “e600 Core to MPX/Platform

Clock PLL Ratio,” for ratio settings.

2. Rise and fall times for SYSCLK are measured at 0.4 and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the short term jitter only and is guaranteed by design.

5. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to allow

cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter. Note that the frequency modulation

for SYSCLK reduces significantly for the spread spectrum source case. This is to guarantee what is supported based on

design.

Table 10. Spread Spectrum Clock Source Recommendations

Parameter

Min

Max

Unit

Notes

Frequency modulation

—

kHz

Frequency spread

—

1.0

1, 2

Notes:

All specifications at recommended operating conditions (see Table 3)

1. Guaranteed by design.

2. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO frequencies, must meet the

minimum and maximum specifications given in Table 10.

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