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MPC8610EC датащи(PDF) 30 Page - Freescale Semiconductor, Inc |
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MPC8610EC датащи(HTML) 30 Page - Freescale Semiconductor, Inc |
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30 / 96 page ![]() MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Electrical Characteristics Freescale Semiconductor 30 2.6.2.2 DDR SDRAM Output AC Timing Specifications Table 22. DDR SDRAM Output AC Timing Specifications At recommended operating conditions. Parameter Symbol1 Min Max Unit Notes MCK[n] cycle time, MCK[n]/MCK[n] crossing tMCK 310 ns 2 MCK duty cycle 533 MHz 400 MHz 333 MHz tMCKH/tMCK 47 47 47 53 53 53 % 8 8 ADDR/CMD output setup with respect to MCK tDDKHAS ns 3 533 MHz 400 MHz 333 MHz 1.48 1.95 2.40 — — — 7 ADDR/CMD output hold with respect to MCK tDDKHAX ns 3 533 MHz 400 MHz 333 MHz 1.48 1.95 2.40 — — — 7 MCS[n] output setup with respect to MCK tDDKHCS ns 3 533 MHz 400 MHz 333 MHz 1.48 1.95 2.40 — — — 7 MCS[n] output hold with respect to MCK tDDKHCX ns 3 533 MHz 400 MHz 333 MHz 1.48 1.95 2.40 — — — 7 MCK to MDQS Skew tDDKHMH –0.6 0.6 ns 4 MDQ/MECC/MDM output setup with respect to MDQS tDDKHDS, tDDKLDS ps 5 533 MHz 400 MHz 333 MHz 590 700 900 — — — 7 MDQ/MECC/MDM output hold with respect to MDQS tDDKHDX, tDDKLDX ps 5 533 MHz 400 MHz 333 MHz 590 700 900 — — — 7 MDQS preamble start tDDKHMP –0.5 × tMCK – 0.6 –0.5 × tMCK +0.6 ns 6 |
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