MPC8610EC datasheet(73/96 Pages) FREESCALE

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Hardware Design Considerations

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

3.1.1

Clock Ranges

Table 53 provides the clocking specifications for the processor core.

Table 54 provides the clocking specifications for the memory bus.

Table 55 provides the clocking specifications for the local bus.

Table 53. Processor Core Clocking Specifications

Characteristic

Maximum Processor Core Frequency

Unit

Notes

800 MHz

1066 MHz

1333 MHz

Min

Max

Min

Max

Min

Max

e600 core processor frequency

666

800

666

1066

666

1333

MHz

1, 2, 3

Notes:

1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting

SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum

operating frequencies. Refer to Section 3.1.2, “Platform/MPX to SYSCLK PLL Ratio” and Section 3.1.3, “e600 Core to

MPX/Platform Clock PLL Ratio,” for ratio settings.

2. The minimum e600 core frequency is based on the minimum platform clock frequency of 333 MHz.

3. The reset config pin cfg_core_speed must be pulled low if the core frequency is 800 MHz or below.

Table 54. Memory Bus Clocking Specifications

Characteristic

Maximum Processor Core

Frequency

Unit

Notes

800, 1066, 1333 MHz

Min

Max

Memory bus clock frequency

166

266

MHz

1, 2

Notes:

1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting

SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum

operating frequencies. Refer to Section 3.1.2, “Platform/MPX to SYSCLK PLL Ratio.”

2. The memory bus clock speed is half the DDR/DDR2 data rate, hence, half the MPX clock frequency.

Table 55. Local Bus Clocking Specifications

Characteristic

Maximum Processor Core

Frequency

Unit

Notes

800, 1066, 1333 MHz

Min

Max

Local bus clock speed

133

MHz

Note:

1. The local bus clock speed on LCLK[0:2] is determined by the MPX clock divided by the local bus ratio programmed in

LCRR[CLKDIV]. Refer to the

MPC8610 Integrated Host Processor Reference Manual, for more information.

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