MPC8610EC datasheet(42/96 Pages) FREESCALE

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MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0

Electrical Characteristics

Freescale Semiconductor

Figure 15 provides the AC test load for the I

2C.

Figure 15. I2C AC Test Load

Noise margin at the HIGH level for each connected device (including

hysteresis)

VNH

0.2

× OVDD

—V

Note:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I

2C timing (I2)

with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high

(H) state or setup time. Also, tI2SXKL symbolizes I

2C timing (I2) for the time that the data with respect to the start condition

(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I

timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock

reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

2. As a transmitter, the MPC8610 provides a delay time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL

signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition.

When MPC8610 acts as the I2C bus master while transmitting, MPC8610 drives both SCL and SDA. As long as the load on

SCL and SDA are balanced, MPC8610 would not cause unintended generation of Start or Stop condition. Therefore, the

300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required

for MPC8610 as transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register to ensure both

the desired I2C SCL clock frequency and SDA output delay time are achieved, assuming that the desired I2C SCL clock

frequency is 400 kHz and the digital filter sampling rate register (I2CDFSRR) is programmed with its default setting of 0x10

(decimal 16):

I2C Source Clock Frequency

533 MHz

400 MHz

333 MHz

266 MHz

FDR Bit Setting

0x0A

0x07

0x2A

0x05

Actual FDR Divider Selected

1536

1024

896

704

Actual I2C SCL Frequency Generated

347 kHz

391 kHz

371 kHz

378 kHz

For the detail of I2C frequency calculation, refer to Freescale application note AN2919,

Determining the I2C Frequency

Divider Ratio for SCL. Note that the I2C source clock frequency is equal to the MPX clock frequency for MPC8610.

3. The maximum tI2DXKL has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.

4. CB = capacitance of one bus line in pF.

5. Guaranteed by design.

Table 31. I2C AC Electrical Specifications (continued)

All values refer to VIH (min) and VIL (max) levels (see Table 30).

Parameter

Symbol1

Min

Max

Unit

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

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