MPC8610EC datasheet(79/96 Pages) FREESCALE

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Hardware Design Considerations

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

Figure 51. Driver Impedance Measurement

Table 60 summarizes the signal impedance targets. The driver impedances are targeted at minimum VDD, nominal OVDD,

105

°C.

3.8

Configuration Pin Muxing

The MPC8610 provides the user with power-on configuration options which can be set through the use of external pull-up or

pull-down resistors of 4.7 k

Ω on certain output pins (see customer visible configuration pins). These pins are generally used as

output only pins in normal operation.

While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is

asserted, is latched when HRESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal

function. Most of these sampled configuration pins are equipped with an on-chip gated resistor of approximately 20 k

Ω. This

value should permit the 4.7-k

Ω resistor to pull the configuration pin to a valid logic low level. The pull-up resistor is enabled

only during HRESET (and for platform /system clocks after HRESET deassertion to ensure capture of the reset value). When

the input receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with minimal signal

quality or delay disruption. The default value for all configuration bits treated this way has been encoded such that a high voltage

level puts the device into the default state and external resistors are needed only when non-default settings are required by the

user.

Careful board layout with stubless connections to these pull-down resistors coupled with the large value of the pull-down

resistor should minimize the disruption of signal quality or speed for output pins thus configured.

The platform PLL ratio and e600 core PLL ratio configuration pins are not equipped with these default pull-up devices.

Table 60. Impedance Characteristics

Impedance

Local Bus, DUART, Control,

Configuration, Power

Management

PCI Express

DDR DRAM

Symbol

Unit

43 Target

25 Target

20 Target

43 Target

25 Target

20 Target

Note: Nominal supply voltages. See Table 3, Tj = 105°C.

OVDD

OGND

Pad

Data

SW1

SW2

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