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MPC8610EC датащи(PDF) 60 Page - Freescale Semiconductor, Inc |
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MPC8610EC датащи(HTML) 60 Page - Freescale Semiconductor, Inc |
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60 / 96 page ![]() MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0 Electrical Characteristics Freescale Semiconductor 60 which requires R2 = 25 Ω. Please consult clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular clock driver chip. Figure 36. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only) Figure 37 shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC levels of the clock driver are compatible with MPC8610 SerDes reference clock input’s DC requirement. Figure 37. Single-Ended Connection (Reference Only) 2.17.2.4 AC Requirements for SerDes Reference Clocks The clock driver selected should provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50 Ω to match the transmission line and reduce reflections which are a source of noise to the system. SD n_REF_CLK SD n_REF_CLK Clock Driver 100 Ω Differential PWB Trace SerDes Refer. CLK Receiver Clock Driver CLK_Out CLK_Out LVPECL CLK Driver Chip R2 R2 MPC8610 10 nF 10 nF CLK_Out CLK_Out R2 R2 R1 Clock Driver 50 Ω 50 Ω R1 SD n_REF_CLK SD n_REF_CLK 100 Ω Differential PWB Trace Clock Driver CLK_Out Single-Ended CLK Driver Chip MPC8610 33 Ω Total 50 Ω. Assume clock driver’s output impedance is about 16 Ω. 50 Ω SerDes Refer. CLK Receiver 50 Ω 50 Ω |
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