MPC8610EC datasheet(84/96 Pages) FREESCALE

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MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0

Hardware Design Considerations

Freescale Semiconductor

Option 2

•

If PCI arbiter is disabled during POR,

— All AD pins will be in the input state. Therefore, all ADs pins need to be grouped together and tied to OVDD

through a single (or multiple) 10-k

Ω resistor(s)

— All PCI control pins can be grouped together and tied to OVDD through a single 10-kΩ resistor

— It is optional to disable PCI block through DEVDISR register after POR reset.

3.12

Thermal

This section describes the thermal specifications of the MPC8610.

3.13

Thermal Characteristics

Table 62 provides the package thermal characteristics for the MPC8610.

3.14

Thermal Management Information

This section provides thermal management information for the flip-chip, plastic ball-grid array (FC_PBGA) package for

air-cooled applications. Proper thermal control design is primarily dependent on the system-level design—the heat sink, airflow,

and thermal interface material. The MPC8610 implements several features designed to assist with thermal management,

including the temperature diode. The temperature diode allows an external device to monitor the die temperature in order to

detect excessive temperature conditions and alert the system; see Section 3.14.5, “Temperature Diode,” for more information.

To reduce the die-junction temperature, heat sinks are required; due to the potential large mass of the heat sink, attachment

through the printed-circuit board is suggested. In any implementation of a heat sink solution, the force on the die should not

exceed ten pounds force (45 newtons). Figure 54 shows a spring clip through the board. Occasionally the spring clip is attached

to soldered hooks or to a plastic backing structure. Screw and spring arrangements are also frequently used.

Table 62. Package Thermal Characteristics1

Characteristic

Symbol

Value

Unit

Notes

Junction-to-ambient thermal resistance, natural convection, single-layer (1s) board

RθJA

°C/W

Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board

RθJA

°C/W

Junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board

RθJMA

°C/W

Junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board

RθJMA

°C/W

Junction-to-board thermal resistance

RθJB

°C/W

Junction-to-case thermal resistance

RθJC

<0.1

°C/W

Notes:

1. Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC

specification for this package.

2. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for

the specified package.

3. Junction-to-case resistance is less than 0.1°C/W because the silicon die is the top of the packaging case..

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