DP83867CSRGZR.B datasheet(119/129 Pages) TI2

119 / 129 page

• Added table note explaining how Duty Cycle % must be interpreted in Section 6.10 ..................................... 12

• Added RGMII TX and RX Latency values in Section 6.10 .............................................................................. 12

• Changed suggestion to program '10M_SGMII_RATE_ADAPT' bit in Section 7.4.1.1 .....................................24

• Changed statement about PHY address in Section 7.4.2 ............................................................................... 27

• Deleted mentions of pin strapping to configure Auto-MDIX in Section 7.4.3.9 ................................................33

• Added Figure 7-9 .............................................................................................................................................33

• Deleted "The BIST allows full control of the packet lengths and of the IPG." from Section 7.4.5 ................... 35

• Deleted mention of ALCD from Section 7.4.6 ..................................................................................................35

• Deleted subsection describing ALCD from Section 7.4.6 ................................................................................35

• Added sentence about the polarity of MDI signals in Section 7.4.6.5 ............................................................. 36

• Changed note after Table 7-6 to be a table note referenced within the table. .................................................38

• Changed 'MMD3_PCS_CTRL' address to 'MMD3' register 0x0000 in Section 7.5.5.5 ...................................44

• Deleted mention of MMD7 in Section 7.5.5.5 ..................................................................................................44

• Added definition for register Bit Name type 'Strap' in Section 7.6 ................................................................... 45

• Deleted Advanced Link Cable Diagnostics Control Register (ALCD_CTRL) .................................................. 45

• Added PAP package default for '1000BASE-T FULL DUPLEX' in Section 7.6.10 .......................................... 55

• Changed 'SGMII_EN' default in Section 7.6.14 ...............................................................................................58

• Changed 'MDI_CROSSOVER' default in Section 7.6.14 ................................................................................ 58

• Added PAP package default for 'SPEED_OPT_EN' in Section 7.6.18 ............................................................65

• Added Section 7.6.28 ...................................................................................................................................... 74

• Changed descriptions of bits 'FORCE_DROP' and 'FLD_EN' in Section 7.6.29 .............................................75

• Added Section 7.6.30 ...................................................................................................................................... 76

• Added 'INT_TST_MODE_1' to Section 7.6.31 ................................................................................................ 76

• Changed 'PORT_MIRROR_EN' default in Section 7.6.31 ...............................................................................76

• Added PAP package default for 'RGMII_EN' in Section 7.6.32 ....................................................................... 76

• Added Section 7.6.36 ...................................................................................................................................... 79

• Changed description of 'STRAP_FLD' from "Fast Link Detect" to "Fast Link Drop" in Section 7.6.39 ............81

• Added Section 7.6.42 ...................................................................................................................................... 82

• Added Section 7.6.43 ...................................................................................................................................... 82

• Changed 'RGMII_TX_DELAY_CTRL' default value in Section 7.6.45 ............................................................ 83

• Changed 'RGMII_RX_DELAY_CTRL' default value in Section 7.6.45 ............................................................ 83

• Added Section 7.6.52 ...................................................................................................................................... 85

• Added Section 7.6.57 ...................................................................................................................................... 86

• Changed description of '10M_SGMIII_RATE_ADAPT' in Section 7.6.103 ......................................................94

• Added GPIO_MUX_CTRL register for RGZ devices........................................................................................96

• Added TDR registers 0x0190 to 0x01A4.......................................................................................................... 97

• Added TDR registers........................................................................................................................................ 97

• Added Section 7.6.130 .................................................................................................................................. 103

• Changed 'PCS_RESET' description in Section 7.6.131 ................................................................................ 103

• Changed capacitor value in Figure 8-2 and added footnotes.........................................................................105

• Added requirements for 2.5V clock source capacitors in Section 8.2.1.2 ..................................................... 107

• Added Figure 8-4 ...........................................................................................................................................107

• Added "RMS Jitter" to Table 8-2 ....................................................................................................................107

• Added Section 8.2.1.4 ................................................................................................................................... 109

• Changed capacitor placement in Figure 8-7 and footnote about decoupling capacitor placement................ 110

• Changed capacitor placement in Figure 8-8 and footnote about decoupling capacitor placement................ 110

Changes from Revision A (February 2017) to Revision B (March 2017)

Page

• Changed pin 6 name in the pinout diagram from: VDDA1P0 to: VDD1P0.........................................................3

• Changed INT / PWDN Interrupt description....................................................................................................... 4

• Changed RESERVED bit number from: 15:8 to: 15:9 ..................................................................................... 76

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DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

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