DP83867CSRGZR.B datasheet(45/129 Pages) TI2

45 / 129 page

7.6 Register Maps

In the register definitions under the ‘Default’ heading, the following definitions hold true:

Read Write access

RW/SC

ReadWrite access/Self Clearing bit

Read Only access

COR

COR = Clear On Read

RO/COR Read Only, Clear On Read

RO/P

Read Only, Permanently set to a default value

Latched Low and held until read, based upon the occurrence of the corresponding event

Latched High and held until read, based upon the occurrence of the corresponding event

Strap

Default value loaded from bootstrap pin after reset

7.6.1 Basic Mode Control Register (BMCR)

Table 7-10. Basic Mode Control Register (BMCR), Address 0x0000

BIT

BIT NAME

DEFAULT

DESCRIPTION

RESET

0, RW/SC

Reset:

1 = Initiate software Reset / Reset in Process.

0 = Normal operation.

This bit, which is self-clearing, returns a value of one until the reset

process is complete. The configuration is restrapped.

LOOPBACK

0, RW

Loopback:

1 = Loopback enabled.

0 = Normal operation.

The loopback function enables MAC transmit data to be routed to

the MAC receive data path.

Setting this bit can cause the descrambler to lose synchronization

and produce a 500µs dead time before any valid data appears at the

MII receive outputs.

SPEED SELECTION LSB

0, RW

Speed Select (Bits 6, 13):

When auto-negotiation is disabled writing to this bit allows the port

speed to be selected.

11 = Reserved

10 = 1000Mbps

1 = 100Mbps

0 = 10Mbps

AUTO-NEGOTIATION ENABLE

Strap, RW

Auto-Negotiation Enable:

Strap controls initial value at reset.

1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are

ignored when this bit is set.

0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port

speed and duplex mode.

POWER DOWN

0, RW

Power Down:

1 = Power down.

0 = Normal operation.

Setting this bit powers down the PHY. Only the register block

is enabled during a power down condition. This bit is ORd with

the input from the PWRDOWN_INT pin. When the active low

PWRDOWN_INT pin is asserted, this bit sets.

www.ti.com

DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

Submit Document Feedback

Product Folder Links: DP83867CS DP83867IS DP83867E

DP83867CSRGZR.B датащи(PDF) 45 Page - Texas Instruments

DP83867CSRGZR.B датащи(HTML) 45 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL