DP83867CSRGZR.B datasheet(44/129 Pages) TI2

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7.5.5.1 Hardware Reset

A hardware reset is accomplished by applying a low pulse, with a duration of at least 1μs, to the RESET_N pin.

This resets the device such that all registers are reinitialized to default values and the hardware configuration

values are re-latched into the device (similar to the power up or reset operation).

7.5.5.2 IEEE Software Reset

An IEEE registers software reset is accomplished by setting the reset bit (bit 15) of the BMCR register (address

0x0000). This bit resets the IEEE-defined standard registers.

7.5.5.3 Global Software Reset

A global software reset is accomplished by setting bit 15 of register CTRL (address 0x001F) to 1. This bit resets

all the internal circuits in the PHY including IEEE-defined registers and all the extended registers. The global

software reset resets the device such that all registers are reset to default values and the hardware configuration

values are maintained.

7.5.5.4 Global Software Restart

A global software restart is accomplished by setting bit 14 of register CTRL (0x001F) to 1. This action resets all

the PHY circuits except the registers in the Register File.

7.5.5.5 PCS Restart

A PCS reset is accomplished by setting bit 15 of register MMD3_PCS_CTRL (MMD3 register 0x0000). Setting

this bit resets the MMD3 register. This bit subsequently cause a soft reset through the BMCR RESET bit (bit 15

of register address 0x0000).

7.5.6 Power-Saving Modes

DP83867 supports 4 power saving modes. The details are provided below.

7.5.6.1 IEEE Power Down

The PHY is powered down but access to the PHY through MDIO-MDC pins is retained. This mode can be

activated by asserting external PWDN pin or by setting bit 11 of BMCR (Register 0x00).

The PHY can be taken out of this mode by a power cycle, software reset, or by clearing the bit 11 in BMCR

remains in power down.

7.5.6.2 Deep Power-Down Mode

This same as IEEE power down but the XI pad is also turned off. This mode can be activated by asserting the

external PWDN pin or by setting bit 11 of BMCR (Register 0x00). Before activating this mode, the configuration

is required to set bit 7 for PHYCR (Register 0x10).

The PHY can be taken out of this mode by a power cycle, software reset or by clearing the bit 11 in BMCR

remains in power down.

7.5.6.3 Active Sleep

In this mode, all the digital and analog blocks are powered down. The PHY is automatically powered up when a

link partner is detected. This mode is useful for saving power when the link partner is down or inactive, but PHY

cannot be powered down. In Active Sleep mode, the PHY still routinely sends NLP to the link partner. This mode

can be active by writing binary 10 to bits [9:8] for PHYCR (Register 0x10).

7.5.6.4 Passive Sleep

This is just like Active sleep except the PHY does not send NLP. This mode can be activated by writing binary 11

to bits [9:8] PHYCR (Register 0x10).

DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

www.ti.com

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