DP83867CSRGZR.B datasheet(27/129 Pages) TI2

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PHY

TX_CTRL

GTX_CLK

TX_D [3:0]

RX_CTRL

RX_CLK

RX_D [3:0]

MAC

Figure 7-6. RGMII Connections

7.4.2 Serial Management Interface

The Serial Management Interface (SMI), provides access to the DP83867 internal register space for status

information and configuration. The SMI is compatible with IEEE 802.3-2002 clause 22. The implemented register

set consists of the registers required by the IEEE 802.3, plus several others to provide additional visibility and

controllability of the DP83867 device.

The SMI includes the MDC management clock input and the management MDIO data pin. The MDC clock is

sourced by the external management entity, also called Station (STA), and can run at a maximum clock rate of

25MHz. MDC is not expected to be continuous, and can be turned off by the external management entity when

the bus is idle.

The MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is latched

on the rising edge of the MDC clock. The MDIO pin requires a pullup resistor (2.2kΩ) which, during IDLE and

turnaround, pulls MDIO high.

Up to 16 PHYs can share a common SMI bus. To distinguish between the PHYs, a 4-bit address is used.

During power-up reset, the DP83867 latches the PHY_ADD configuration pins to determine the address. The

DP83867IRPAP 64-pin variant can support up to 32 PHYs and uses a 5-bit address.

The management entity must not start an SMI transaction in the first cycle after power-up reset. To maintain valid

operation, the SMI bus must remain inactive at least one MDC cycle after hard reset is deasserted. In normal

MDIO transactions, the register address is taken directly from the management-frame reg_addr field, thus

allowing direct access to 32 16-bit registers (including those defined in IEEE 802.3 and vendor specific). The

data field is used for both reading and writing. The Start code is indicated by a <01> pattern. This pattern makes

sure that the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit time

inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no

device can actively drive the MDIO signal during the first bit of turnaround. The addressed DP83867 drives the

MDIO with a zero for the second bit of turnaround and follows this with the required data. Figure 7-7 shows the

timing relationship between MDC and the MDIO as driven and received by the Station (STA) and the DP83867

(PHY) for a typical register read access.

For write transactions, the station-management entity writes data to the addressed DP83867, thus eliminating

the requirement for MDIO turnaround. The turnaround time is filled by the management entity by inserting <10>.

Figure 7-7 shows the timing relationship for a typical MII register write access. The frame structure and general

read and write transactions are shown in Table 7-2, Figure 7-7, and Figure 7-8.

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DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

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