DP83867CSRGZR.B datasheet(23/129 Pages) TI2

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7.3.2.1.1 1000Mb SFD Variation in Master Mode

When the DP83867 is operating in 1000Mb master mode, variation of the RX_SFD pulse can be estimated using

the Skew FIFO Status register (register address 0x0055) bit[7:4]. The value read from the Skew FIFO Status

Example: While operating in master 1000Mb mode, a value of 0x2 is read from the Skew FIFO register bit[7:4].

2 × 8ns = 16ns is subtracted from the TX_SFD to RX_SFD measurement to determine the baseline latency.

7.3.2.1.2 1000Mb SFD Variation in Slave Mode

When the DP83867 is operating in 1000Mb slave mode, the variation of the RX_SFD pulse can be determined

using the Skew FIFO Status register (register address 0x0055) bit[3:0].The value read from the Skew FIFO

Status register bit[3:0] can be multiplied by 8ns to estimate the RX_SFD variation added to the baseline latency.

Example: While operating in slave 1000Mb mode, a value of 0x1 is read from the Skew FIFO register bit[3:0].

1 × 8ns = 8ns is subtracted from the TX_SFD to RX_SFD measurement to determine the baseline latency.

7.3.2.1.3 100Mb SFD Variation

The latency variation in 100Mb mode of operation is determined by random process and does not require any

7.3.3 Clock Output

The DP83867 has several internal clocks, including the local reference clock, the Ethernet transmit clock, and

the Ethernet receive clock. An external crystal or oscillator provides the stimulus for the local reference clock.

The local reference clock acts as the central source for all clocking in the device.

The local reference clock is embedded into the transmit network packet traffic and is recovered from the network

packet traffic at the receiver node. The receive clock is recovered from the received Ethernet packet data stream

and is locked to the transmit clock in the partner.

Using the I/O Configuration register (address 0x0170), the DP83867 can be configured to output these internal

clocks through the CLK_OUT pin. By default, the output clock is synchronous to the XI oscillator / crystal input.

The default output clock is suitable for use as the reference clock of another DP83867 device. Through registers,

the output clock can be configured to be synchronous to the receive data at the 125MHz data rate or at the

divide by 5 rate of 25MHz. It can also be configured to output the line driver transmit clock. When operating in

1000Base-T mode, the output clock can be configured for any of the four transmit or receive channels.

The output clock can be disabled using the CLK_O_DISABLE bit of the I/O Configuration register.

7.4 Device Functional Modes

7.4.1 MAC Interfaces

The DP83867 supports connection to an Ethernet MAC through the following interfaces: SGMII and RGMII.

The SGMII Enable (LED_0) strap allows the user to turn the SGMII MAC interface on or off. The SGMII Enable

strap corresponds to the SGMII Enable (bit 11) in the PHYCR register (address 0x0010).

The SGMII enable has higher priority than the RGMII enable. Table 7-1 is the configuration table for the MAC

interfaces:

Table 7-1. Configuration Table for the MAC Interfaces

SGMII ENABLE (REGISTER 0x0010, BIT

11)

RGMII ENABLE (REGISTER 0x0032, BIT 7)

DEVICE FUNCTIONAL MODE

0x1

SGMII

0x1

0x0

SGMII

0x0

0x1

RGMII

The initial strap values for the SGMII enable and the RGMII disable are also available in the Strap Configuration

Status Register 1 (STRAP_STS1).

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DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

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