DP83867CSRGZR.B datasheet(42/129 Pages) TI2

номер детали	DP83867CSRGZR.B

подробное описание детали	DP83867E/IS/CS Robust, High Immunity, Small Form Factor 10/100/1000 Ethernet Physical Layer Transceiver

PDF	129 Pages

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производитель	TI2 [Texas Instruments]

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7.5.3 LED Operation From 1.8V I/O VDD Supply

Operation of LEDs from a 1.8V supply results in dim LED lighting. For best results, the recommendation is

to operate from a higher supply (2.5V or 3.3V). Refer to Figure 7-12 for a possible implementation of this

functionality.

10 NŸ

200 Ÿ

GND

Mode 2

2.5V or 3.3V

2.49 NŸ

GND

1.8V

Figure 7-12. LED Operation From 1.8V I/O VDD Supply

7.5.4 PHY Address Configuration

The DP83867 can be set to respond to any of 16 possible PHY addresses through strap pins. The information is

latched into the device at a device power up or hardware reset. Each DP83867 or port sharing an MDIO bus in a

system must have a unique physical address. The DP83867 supports PHY address strapping values 0 (<0000>)

through 15 (<1111>).

For further detail relating to the latch-in timing requirements of the PHY Address pins, as well as the other

hardware configuration pins, refer to Section 7.5.5.

Based on the default strap configuration of PHY_ADD[3:0], the DP83867 PHY address initializes to 0x00 without

any external strap configuration.

Refer to Figure 7-13 for an example of a PHY address connection to external components. In this example, the

pins are configured as follows: RX_D2 = Strap Mode 3 and RX_D0 = Strap Mode 2. Therefore, the PHY address

strapping results in address 1001 (09h).

DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

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DP83867CSRGZR.B датащи(PDF) 42 Page - Texas Instruments