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DP83867CSRGZR.B датащи(PDF) 61 Page - Texas Instruments

номер детали DP83867CSRGZR.B
подробное описание детали  DP83867E/IS/CS Robust, High Immunity, Small Form Factor 10/100/1000 Ethernet Physical Layer Transceiver
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DP83867CSRGZR.B датащи(HTML) 61 Page - Texas Instruments

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7.6.16 MII Interrupt Control Register (MICR)
This register implements the Interrupt PHY Specific Control register. The individual interrupt events must be
enabled by setting bits in the MII Interrupt Control Register (MICR). If the corresponding enable bit in the register
is set, an interrupt is generated if the event occurs.
Table 7-26. MII Interrupt Control Register (MICR), Address 0x0012
BIT
BIT NAME
DEFAULT
DESCRIPTION
15
AUTONEG_ERR_INT_EN
0, RW
Enable Auto-Negotiation Error Interrupt:
1 = Enable Auto-Negotiation Error interrupt.
0 = Disable Auto-Negotiation Error interrupt.
14
SPEED_CHNG_INT_EN
0, RW
Enable Speed Change Interrupt:
1 = Enable Speed Change interrupt.
0 = Disable Speed Change interrupt.
13
DUPLEX_MODE_CHNG_INT_E
N
0, RW
Enable Duplex Mode Change Interrupt:
1 = Enable Duplex Mode Change interrupt.
0 = Disable Duplex Mode Change interrupt.
12
PAGE_RECEIVED_INT_EN
0, RW
Enable Page Received Interrupt:
1 = Enable Page Received Interrupt.
0 = Disable Page Received Interrupt.
11
AUTONEG_COMP_INT_EN
0, RW
Enable Auto-Negotiation Complete Interrupt:
1 = Enable Auto-Negotiation Complete Interrupt.
0 = Disable Auto-Negotiation Complete Interrupt.
10
LINK_STATUS_CHNG_INT_EN
0, RW
Enable Link Status Change Interrupt:
1 = Enable Link Status Change interrupt.
0 = Disable Link Status Change interrupt.
9
RESERVED
0, RO
RESERVED
8
FALSE_CARRIER_INT_EN
0, RW
Enable False Carrier Interrupt:
1 = Enable False Carrier interrupt.
0 = Disable False Carrier interrupt.
7
RESERVED
0, RO
RESERVED
6
MDI_CROSSOVER_CHNG_INT_
EN
0, RW
Enable MDI Crossover Change Interrupt:
1 = Enable MDI Crossover Change interrupt.
0 = Disable MDI Crossover Change interrupt.
5
SPEED_OPT_EVENT_INT_EN
0, RW
Enable Speed Optimization Event Interrupt:
1 = Enable Speed Optimization Event Interrupt.
0 = Disable Speed Optimization Event Interrupt.
4
SLEEP_MODE_CHNG_INT_EN
0, RW
Enable Sleep Mode Change Interrupt:
1 = Enable Sleep Mode Change Interrupt.
0 = Disable Sleep Mode Change Interrupt.
3
WOL_INT_EN
0, RW
Enable Wake-on-LAN Interrupt:
1 = Enable Wake-on-LAN Interrupt.
0 = Disable Wake-on-LAN Interrupt.
www.ti.com
DP83867CS, DP83867IS, DP83867E
SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025
Copyright © 2025 Texas Instruments Incorporated
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Product Folder Links: DP83867CS DP83867IS DP83867E



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