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DP83867CSRGZR.B датащи(PDF) 93 Page - Texas Instruments

номер детали DP83867CSRGZR.B
подробное описание детали  DP83867E/IS/CS Robust, High Immunity, Small Form Factor 10/100/1000 Ethernet Physical Layer Transceiver
PDF  129 Pages
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производитель  TI2 [Texas Instruments]
домашняя страница  https://www.ti.com
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DP83867CSRGZR.B датащи(HTML) 93 Page - Texas Instruments

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7.6.91 Receive Pattern Register 26 (RXFPAT26)
Table 7-101. Receive Pattern Register 26 (RXFPAT26), Address 0x0155
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:0
PATTERN_BYTES_50_51
0, RW
Bytes 50 + 51 of the configured pattern. Each byte can be masked
separately through the RXF_PATTERN_BYTE_MASK registers.
7.6.92 Receive Pattern Register 27 (RXFPAT27)
Table 7-102. Receive Pattern Register 27 (RXFPAT27), Address 0x0156
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:0
PATTERN_BYTES_52_53
0, RW
Bytes 52 + 53 of the configured pattern. Each byte can be masked
separately through the RXF_PATTERN_BYTE_MASK registers.
7.6.93 Receive Pattern Register 28 (RXFPAT28)
Table 7-103. Receive Pattern Register 28 (RXFPAT28), Address 0x0157
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:0
PATTERN_BYTES_54_55
0, RW
Bytes 54 + 55 of the configured pattern. Each byte can be masked
separately through the RXF_PATTERN_BYTE_MASK registers.
7.6.94 Receive Pattern Register 29 (RXFPAT29)
Table 7-104. Receive Pattern Register 29 (RXFPAT29), Address 0x0158
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:0
PATTERN_BYTES_56_57
0, RW
Bytes 56 + 57 of the configured pattern. Each byte can be masked
separately through the RXF_PATTERN_BYTE_MASK registers.
7.6.95 Receive Pattern Register 30 (RXFPAT30)
Table 7-105. Receive Pattern Register 30 (RXFPAT30), Address 0x0159
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:0
PATTERN_BYTES_58_59
0, RW
Bytes 58 + 59 of the configured pattern. Each byte can be masked
separately through the RXF_PATTERN_BYTE_MASK registers.
7.6.96 Receive Pattern Register 31 (RXFPAT31)
Table 7-106. Receive Pattern Register 31 (RXFPAT31), Address 0x015A
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:0
PATTERN_BYTES_0_1
0, RW
Bytes 60 + 61 of the configured pattern. Each byte can be masked
separately through the RXF_PATTERN_BYTE_MASK registers.
7.6.97 Receive Pattern Register 32 (RXFPAT32)
Table 7-107. Receive Pattern Register 32 (RXFPAT32), Address 0x015B
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:0
PATTERN_BYTES_62_63
0, RW
Bytes 62 + 63 of the configured pattern. Each byte can be masked
separately through the RXF_PATTERN_BYTE_MASK registers.
7.6.98 Receive Pattern Byte Mask Register 1 (RXFPBM1)
Table 7-108. Receive Pattern Byte Mask Register 1 (RXFPBM1), Address 0x015C
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:0
PATTERN_BYTES_ MASK_0_15 0, RW
Masks for bytes 0 to 15 of the pattern. A 1 indicates a mask for the
associated byte.
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DP83867CS, DP83867IS, DP83867E
SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025
Copyright © 2025 Texas Instruments Incorporated
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