DP83867CSRGZR.B datasheet(77/129 Pages) TI2

77 / 129 page

Table 7-42. RGMII Control Register (RGMIICTL), Address 0x0032 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

RGMII_TX_CLK_DELAY

1, RW

RGMII Transmit Clock Delay:

1 = RGMII transmit clock is shifted relative to transmit data.

0 = RGMII transmit clock is aligned to transmit data.

RGMII_RX_CLK_DELAY

1, RW

RGMII Receive Clock Delay:

1 = RGMII receive clock is shifted relative to receive data.

0 = RGMII receive clock is aligned to receive data.

7.6.33 RGMII Control Register 2 (RGMIICTL2)

Table 7-43. RGMII Control Register 2 (RGMIICTL2), Address 0x0033

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:5

RESERVED

0, RO

RESERVED

RGMII_AF_BYPASS_EN

0, RW

RGMII Async FIFO Bypass Enable:

1 = Enable RGMII Async FIFO Bypass.

0 = Normal operation.

RGMII_AF_BYPASS_DLY_EN

0, RW

RGMII Async FIFO Bypass Delay Enable:

1 = Delay RX_CLK when operating in 10/100 with RGMII.

0 = Normal operation.

LOW_LATENCY_10_100_EN

0, RW

Low Latency 10/100 Enable:

1 = Enable low latency in 10/100 operation.

0 = Normal operation.

1:0

RESERVED

0, RO

RESERVED

7.6.34 SGMII Auto-Negotiation Status (SGMII_ANEG_STS)

Table 7-44. SGMII Auto-Negotiation Status (SGMII_ANEG_STS)), address 0x0037

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:2

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

SGMII_PAGE_RX

0, RO

SGMII Page Received:

1 = SGMII page has been received.

0 = SGMII page has not been received.

SGMII_AUTONEG_COMPLETE

0, RO

SGMII Auto-Negotiation Complete:

1 = SGMII Auto-Negotiation process complete.

0 = SGMII Auto-Negotiation process not complete.

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DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

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