DP83867CSRGZR.B datasheet(56/129 Pages) TI2

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7.6.11 Status Register 1 (STS1)

Table 7-20. Status Register 1 (STS1) Address 0x000A

BIT

BIT NAME

DEFAULT

DESCRIPTION

MASTER / SLAVE

CONFIGURATION FAULT

0, RO, LH, COR Master / Slave Manual Configuration Fault Detected:

1 = Manual Master/Slave Configuration fault detected.

0 = No Manual Master/Slave Configuration fault detected.

MASTER / SLAVE

CONFIGURATION

RESOLUTION

0, RO

Master / Slave Configuration Results:

1 = Configuration resolved to MASTER.

0 = Configuration resolved to SLAVE.

LOCAL RECEIVER STATUS

0, RO

Local Receiver Status:

1 = Local receiver is OK.

0 = Local receiver is not OK.

REMOTE RECEIVER STATUS

0, RO

Remote Receiver Status:

1 = Remote receiver is OK.

0 = Remote receiver is not OK.

1000BASE-T FULL DUPLEX

0, RO

Link Partner 1000BASE-T Full Duplex Capable:

1 = Link Partner capable of 1000Base-T Full Duplex.

0 = Link partner not capable of 1000Base-T Full Duplex.

1000BASE-T HALF DUPLEX

0, RO

Link Partner 1000BASE-T Half Duplex Capable:

1 = Link Partner capable of 1000Base-T Half Duplex.

0 = Link partner not capable of 1000Base-T Half Duplex.

9:8

RESERVED

00, RO

RESERVED by IEEE: Writes ignored, read as 0.

7:0

IDLE ERROR COUNTER

0000 0000, RO,

COR

1000BASE-T Idle Error Counter

7.6.12 Extended Register Addressing

REGCR (0x000D) and ADDAR (0x000E) allow read/write access to the extended register set (addresses above

0x001F) using indirect addressing.

• REGCR [15:14] = 00: A write to ADDAR modifies the extended register set address register. This address

• •REGCR [15:14] = 01: A read or write to ADDAR operates on the register within the extended register set

selected (pointed to) by the value in the address register. The address register contents (pointer) remain

unchanged.

• REGCR [15:14] = 10: A read or write to ADDAR operates on the register within the extended register set

selected (pointed to) by the value in the address register. After that access is complete, for both reads and

writes, the value in the address register is incremented.

• REGCR [15:14] = 11: A read or write to ADDAR operates on the register within the extended register set

selected (pointed to) by the value in the address register. After that access is complete, for write accesses

only, the value in the address register is incremented. For read accesses, the value of the address register

remains unchanged.

DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

www.ti.com

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