DP83867CSRGZR.B datasheet(76/129 Pages) TI2

76 / 129 page

7.6.30 Fast Link Drop Threshold Configuration Register (FLD_THR_CFG)

Table 7-40. Fast Link Drop Threshold Configuration Register (FLD_THR_CFG), Address 0x002E

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:11

RESERVED

0, RO

RESERVED

10:8

RESERVED

0x2, RW

RESERVED

0, RO

RESERVED

6:4

RESERVED

0x2, RW

RESERVED

0, RO

RESERVED

2:0

ENERGY_LOST_FLD_THR

0x1, RW

Energy Lost Threshold for FLD Energy Lost Mode

ENERGY_LOST_FLD_THR asserts if energy detector accumulator

falls below this threshold. When using strap to enable FLD feature,

this bit defaults to 0x2. Register write is needed to change the value

to 0x1. Changing the field to other value is not advised.

7.6.31 Configuration Register 4 (CFG4)

Table 7-41. Configuration Register 4 (CFG4), Address 0x0031

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:13

RESERVED

000, RO

RESERVED

1, RO

RESERVED

11:9

RESERVED

000, RO

RESERVED

0, RW

RESERVED

INT_TST_MODE_1

Strap, RW

Reserved; 0: Normal Operation.

If RX_CTRL is strapped to mode1/mode2 then PHY goes to internal

test mode. Reg x6F[8] = 0 also indicates the test mode entry request

from RX_CTRL's strap . To overrule this test mode entry through

strap mode, INT_TST_MODE_1bit can be set to 0.

1: Internal Test Mode 1, this bit must be cleared

0: Normal Operation

6:5

SGMII_AUTONEG_TIMER

01, RW

SGMII Auto-Negotiation Timer Duration:

11: 11ms

10: 800µs

01: 2µs

00: 16ms

4:1

RESERVED

1000, RO

RESERVED: Writes ignored, read as 1000.

PORT_MIRROR_EN

Strap, RW

Port Mirror Enable:

1 = Enable port mirroring.

0 = Normal operation

7.6.32 RGMII Control Register (RGMIICTL)

This register provides access to the RGMII controls.

Table 7-42. RGMII Control Register (RGMIICTL), Address 0x0032

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

RGMII_EN

RGZ: 1, RW

RGMII Enable:

1 = Enable RGMII interface.

0 = Disable RGMII interface.

PAP: Strap, RW

6:5

RGMII_RX_HALF_FULL_THR

10, RW

RGMII Receive FIFO Half Full Threshold:

This field controls the RGMII receive FIFO half full threshold.

4:3

RGMII_TX_HALF_FULL_THR

10, RW

RGMII Transmit FIFO Half Full Threshold:

This field controls the RGMII transmit FIFO half full threshold.

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

www.ti.com

Submit Document Feedback

Product Folder Links: DP83867CS DP83867IS DP83867E

DP83867CSRGZR.B датащи(PDF) 76 Page - Texas Instruments

DP83867CSRGZR.B датащи(HTML) 76 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL