DP83867CSRGZR.B datasheet(24/129 Pages) TI2

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7.4.1.1 Serial GMII (SGMII)

The Serial Gigabit Media Independent Interface (SGMII) provides a means of conveying network data and port

speed between a 100/1000 PHY and a MAC with significantly less signal pins (4 or 6 pins) than required for

GMII (24 pins) or RGMII (12 pins). The SGMII interface uses 1.25-Gbps LVDS differential signaling which has

the added benefit of reducing EMI emissions relative to GMII or RGMII.

Because the internal clock and data recovery circuitry (CDR) of DP83867 can detect the transmit timing of

the SGMII data, TX_CLK is not required. SGMII interface is capable of working as a 4-wire or 6-wire SGMII

interface. The default SGMII connection is through four wires. Two differential pairs are used for the transmit

and receive connections. Clock and data recovery are performed in the MAC and in the PHY, so no additional

differential pair is required for clocking. Alternately, if the MAC is not capable of recovering the clock from the

SGMII receive data, the DP83867 can be configured to provide the SGMII receive clock through a differential

pair.

The 1.25-Gbps rate of SGMII is excessive for 100Mbps operation. When operating in 100Mbps mode, the PHY

elongates the frame by replicating each frame byte 10 times. This frame elongation takes place above the IEEE

802.3 PCS layer, thus the start of frame delimiter only appears once per frame.

The SGMII interface includes Auto-Negotiation capability. Auto-Negotiation provides a mechanism for control

information to be exchanged between the PHY and the MAC. This allows the interface to be automatically

configured based on the media speed mode resolution on the MDI side. In MAC loopback mode, the SGMII

speed is determined by the MDI speed selection. The SGMII interface works in both Auto-Negotiation and forced

speed mode during the MAC loopback operation. SGMII Auto-Negotiation is the default mode of the operation.

The SGMII Auto-Negotiation process can be disabled and the SGMII speed mode can be forced to the MDI

resolved speed. The SGMII forced speed mode can be enabled with the MDI auto-negotiation or MDI manual

speed mode. SGMII Auto-Negotiation can be disabled through the SGMII_AUTONEG_EN register bit in the

CFG2 register (address 0x0014).

The 10M_SGMII_RATE_ADAPT bit (bit 7) does not need to be changed for 10M speed as the PHY

automatically adapts the rate of SGMII.

SGMII is enabled through a resistor strap option. See Section 7.5.1 for details.

All SGMII connections must be AC-coupled through an 0.1µF capacitor. PHY has inbuilt 100Ω differential

termination at receive and transmit pins of SGMII.

The connection diagrams for 4-wire SGMII and 6-wire SGMII are shown in Figure 7-4 and Figure 7-5.

DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

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DP83867CSRGZR.B датащи(PDF) 24 Page - Texas Instruments