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DP83867CSRGZR.B датащи(PDF) 67 Page - Texas Instruments |
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DP83867CSRGZR.B датащи(HTML) 67 Page - Texas Instruments |
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67 / 129 page ![]() Table 7-30. BIST Control Register (BISCR), Address 0x0016 (continued) BIT BIT NAME DEFAULT DESCRIPTION 1:0 PCS_LOOPBACK 0, RW PCS Loopback Select: When configured for 100Base-TX: 11: Loop after MLT3 encoder (full TX/RX path) 10: Loop after scrambler, before MLT3 encoder 01: Loop before scrambler When configured for 1000Base-T: x1: Loop before 1000Base-T signal processing. 7.6.21 Status Register 2 (STS2) Table 7-31. Status Register 2 (STS2), Address 0x0017 BIT BIT NAME DEFAULT DESCRIPTION 15:12 RESERVED 0, RO RESERVED: Writes ignored, read as 0. 11 PRBS_LOCK 0, RO PRBS Lock Status: 1 = PRBS checker is locked to the received byte stream. 0 = PRBS checker is not locked. 10 PRBS_LOCK_LOST 0, RO, LH, COR PRBS Lock Lost: 1 = PRBS checker has lost lock. 0 = PRBS checker has not lost lock. 9 PKT_GEN_BUSY 0, RO Packet Generator Busy: 1 = Packet generation is in process. 0 = Packet generation is not in process. 8 SCR_MODE_MASTER_1G 0, RO Gigabit Master Scramble Mode: 1 = 1G PCS (master) is in legacy encoding mode. 0 = 1G PCS (master) is in normal encoding mode.. 7 SCR_MODE_MASTER_1G 0, RO Gigabit Slave Scramble Mode: 1 = 1G PCS (slave) is in legacy encoding mode. 0 = 1G PCS (slave) is in normal encoding mode.. 6 CORE_PWR_MODE 0, RO Core Power Mode: 1 = Core is in normal power mode. 0 = Core is power-down mode or in sleep mode. 5:0 RESERVED 0, RO RESERVED: Writes ignored, read as 0. www.ti.com DP83867CS, DP83867IS, DP83867E SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 67 Product Folder Links: DP83867CS DP83867IS DP83867E |
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