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DP83867CSRGZR.B датащи(PDF) 79 Page - Texas Instruments

номер детали DP83867CSRGZR.B
подробное описание детали  DP83867E/IS/CS Robust, High Immunity, Small Form Factor 10/100/1000 Ethernet Physical Layer Transceiver
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DP83867CSRGZR.B датащи(HTML) 79 Page - Texas Instruments

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7.6.36 Viterbi Module Configuration (VTM_CFG)
Table 7-46. Viterbi Module Configuration (VTM_CFG), Address 0x0053
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:4
RESERVED
0x205, RO
RESERVED
3:0
VTM_IDLE_CHECK_CNT_THR
0x5, RW
Viterbi Detector Idle Count Threshold
Threshold for consecutive amount of Idle symbols for Viterbi Idle
detector to assert Idle Mode.
Default value 0x5 is for IPG >= 12. Set this field to 0x4: for IPG < 12.
Please verify new register settings through system level tests if this
field is changed.
7.6.37 Skew FIFO Status (SKEW_FIFO)
Table 7-47. Skew FIFO Status (SKEW_FIFO), Address 0x0055
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:8
RESERVED
0, RO
RESERVED
7:4
CH_B_SKEW
0, RO
Skew of RX channel B to align symbols in # of clock cycles.
3:0
CH_A_SKEW
0, RO
Skew of RX channel A to align symbols in # of clock cycles.
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DP83867CS, DP83867IS, DP83867E
SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025
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