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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DP83867CSRGZR.B датащи(PDF) 81 Page - Texas Instruments |
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DP83867CSRGZR.B датащи(HTML) 81 Page - Texas Instruments |
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81 / 129 page  7.6.39 Strap Configuration Status Register 2 (STRAP_STS2) Table 7-49. Strap Configuration Status Register 2 (STRAP_STS2), Address 0x006F BIT BIT NAME DEFAULT DESCRIPTION 15:11 RESERVED 0, RO RESERVED 10 STRAP_ FLD Strap, RO Fast Link Drop (FLD) Enable Strap: 1 = FLD strapped to enable. 0 = FLD strapped to disable. 10 RESERVED 0, RO RESERVED 9 RESERVED 0, RO RESERVED 8 RESERVED 0, RO RESERVED 7 RESERVED 0, RO RESERVED 6:4 STRAP_RGMII_CLK_SKEW_TX (RGZ) Strap, RO RGMII Transmit Clock Skew Strap: RGMII_TX_DELAY_CTRL[2:0] values from straps. See RGMII Transmit Clock Skew Details table for more information. 6:4 STRAP_RGMII_CLK_SKEW_TX Strap, RO RGMII Transmit Clock Skew Strap: RGMII_TX_DELAY_CTRL[2:0] values from straps. See RGMII Transmit Clock Skew Details table for more information. 3 RESERVED 0, RO RESERVED 2:0 STRAP_RGMII_CLK_SKEW_RX Strap, RO RGMII Receive Clock Skew Strap: RGMII_RX_DELAY_CTRL[2:0] values from straps. See Table 7-8 for more information. 7.6.40 BIST Control and Status Register 1 (BICSR1) Table 7-50. BIST Control and Status Register 1 (BICSR1), Address 0x0071 BIT BIT NAME DEFAULT DESCRIPTION 15:0 PRBS_BYTE_CNT 0x0000, RO Holds the number of total bytes received by the PRBS checker. Value in this register is locked when write is done to register BICSR2 bit[0] or bit[1]. The count stops at 0xFFFF when PRBS_COUNT_MODE in BISCR register (0x0016) is set to 0. 7.6.41 BIST Control and Status Register 2 (BICSR2) Table 7-51. BIST Control and Status Register 2 (BICSR2), Address 0x0072 BIT BIT NAME DEFAULT DESCRIPTION 15:11 Reserved 0x00, RO Ignored on Read 10 PRBS_PKT_CNT_OVF 0, RO PRBS Checker Packet Count Overflow If set, PRBS Packet counter has reached overflow. Overflow is cleared when PRBS counters are cleared by setting bit #1 of this register. 9 PRBS_BYTE_CNT_OVF 0, RO PRBS Byte Count Overflow If set, PRBS Byte counter has reached overflow. Overflow is cleared when PRBS counters are cleared by setting bit #1 of this register. 8 Reserved 0,RO Ignore on Read 7:0 PRBS_ERR_CNT 0x00, RO Holds number of error bytes that are received by PRBS checker. Value in this register is locked when write is done to bit[0] or bit[1] When PRBS Count Mode set to zero, count stops on 0xFF (see register 0x0016) Notes: Writing bit 0 generates a lock signal for the PRBS counters. Writing bit 1 generates a lock and clear signal for the PRBS counters www.ti.com DP83867CS, DP83867IS, DP83867E SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 81 Product Folder Links: DP83867CS DP83867IS DP83867E |
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