DP83867CSRGZR.B datasheet(58/129 Pages) TI2

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7.6.14 PHY Control Register (PHYCR)

Table 7-24. PHY Control Register (PHYCR), Address 0x0010

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:14

TX FIFO Depth

1, RW

TX FIFO Depth:

11 = 8 bytes/nibbles (1000Mbps/Other Speeds)

10 = 6 bytes/nibbles (1000Mbps/Other Speeds)

01 = 4 bytes/nibbles (1000Mbps/Other Speeds)

00 = 3 bytes/nibbles (1000Mbps/Other Speeds)

Note: FIFO is enabled only in the following modes:

1000BaseT + GMII

10BaseT/100BaseTX/1000BaseT + SGMII

13:12

RX FIFO Depth

1, RW

RX FIFO Depth:

11 = 8 bytes/nibbles (1000Mbps/Other Speeds)

10 = 6 bytes/nibbles (1000Mbps/Other Speeds)

01 = 4 bytes/nibbles (1000Mbps/Other Speeds)

00 = 3 bytes/nibbles (1000Mbps/Other Speeds)

Note: FIFO is enabled only in SGMII

SGMII_EN

Strap, RW

SGMII Enable:

1 = Enable SGMII

0 = Disable SGMII

FORCE_LINK_GOOD

0, RW

Force Link Good:

1 = Force link good according to the selected speed.

0 = Normal operation

9:8

POWER_SAVE_MODE

0, RW

Power-Saving Modes:

11 = Passive Sleep mode: Power down all digital and analog blocks.

10 =Active Sleep mode: Power down all digital and analog blocks.

Automatic power-up is performed when link partner is detected. Link

pulses are transmitted approximately once per 1.4 Sec in this mode

to wake up any potential link partner.

01 = IEEE mode: power down all digital and analog blocks.

Note: If DISABLE_CLK_125 (bit [4]of this register) is set to zero, the

PLL is also powered down.

00 = Normal mode

DEEP_POWER_DOWN_EN

0, RW

Deep power-down mode enable

1 = When power down is initiated through assertion of the external

power-down pin or through the POWER_DOWN bit in the BMCR, the

device enters a deep power-down mode.

0 = Normal operation.

6:5

MDI_CROSSOVER

RGZ: 10, RW

MDI Crosssover Mode:

1x = Enable automatic crossover

01 = Manual MDI-X configuration

00 = Manual MDI configuration

PAP: Strap, RW

DISABLE_CLK_125

0, RW

Disable 125MHz Clock:

This bit can be used in conjunction with POWER_SAVE_MODE (bits

9:8 of this register).

1 = Disable CLK125.

0 = Enable CLK125.

RESERVED

1, RO

RESERVED: Writes ignored, read as 1.

STANDBY_MODE

0, RW

Standby Mode:

1 = Enable standby mode. Digital and analog circuitry are powered

up, but no link can be established.

0 = Normal operation.

LINE_DRIVER_INV_EN

0, RW

Line Driver Inversion Enable:

1 = Invert Line Driver Transmission.

0 = Normal operation.

DISABLE_JABBER

0, RW

Disable Jabber

1 = Disable Jabber function.

0 = Enable Jabber function.

DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

www.ti.com

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