SC16C852LIB datasheet(27/60 Pages) PHILIPS

27 / 60 page

SC16C852L_2

Product data sheet

Rev. 02 — 25 January 2007

27 of 60

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

[1]

For 128-byte FIFO mode, refer to Section 7.16, Section 7.17, Section 7.18.

[2]

For 128-byte FIFO mode, refer to Section 7.15, Section 7.17, Section 7.18.

[1]

When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and

transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see Section 6.4 “FIFO operation”).

[1]

When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and

transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see Section 6.4 “FIFO operation”).

(cont.)

Transmit operation in mode ‘1’: When the SC16C852L is in FIFO mode

(FCR[0] = logic 1; FCR[3] = logic 1), the TXRDYA/TXRDYB pin will be a

logic 1 when the transmit FIFO is completely full; see Section 6.10 “DMA

operation”. It will be a logic 0 when the trigger level has been reached.

Receive operation in mode ‘1’: When the SC16C852L is in FIFO mode

(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached,

or a Receive Time-Out has occurred, the RXRDYA/RXRDYB pin will go to a

logic 0. Once activated, it will go to a logic 1 after there are no more

characters in the FIFO.

FCR[2]

XMIT FIFO reset.

logic 0 = no FIFO transmit reset (normal default condition)

logic 1 = clears the contents of the transmit FIFO and resets the FIFO

counter logic. This bit will return to a logic 0 after clearing the FIFO.

FCR[1]

RCVR FIFO reset.

logic 0 = no FIFO receive reset (normal default condition)

logic 1 = clears the contents of the receive FIFO and resets the FIFO

counter logic. This bit will return to a logic 0 after clearing the FIFO.

FCR[0]

FIFO enable.

logic 0 = disable the transmit and receive FIFO (normal default condition)

logic 1 = enable the transmit and receive FIFO

Table 13.

RCVR trigger levels

FCR[7]

FCR[6]

RX FIFO trigger level (bytes) in 32-byte FIFO mode[1]

008

0116

1024

1128

Table 14.

TX FIFO trigger levels

FCR[5]

FCR[4]

TX FIFO trigger level (bytes) in 32-byte FIFO mode[1]

0016

018

1024

1130

Table 12.

FIFO Control Register bits description …continued

Bit

Symbol

Description

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