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SC16C852LIB датащи(PDF) 46 Page - NXP Semiconductors |
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SC16C852LIB датащи(HTML) 46 Page - NXP Semiconductors |
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46 / 60 page ![]() SC16C852L_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 25 January 2007 46 of 60 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder (1) INT is active when RX FIFO fills up to trigger level or a time-out condition happens (see Section 6.8). (2) INT is cleared when RX FIFO drops below trigger level. Fig 16. Receive timing in 16 mode D0 D1 D2 D3 D4 D5 D6 D7 active active 16 baud rate clock 002aac612 RXA, RXB INT(1)(2) IOR td(IOR-INTL) td(stop-INT) 5 data bits 6 data bits 7 data bits stop bit parity bit start bit data bits (0 to 7) next data start bit (1) IRQ is active when RX FIFO fills up to trigger level or time-out condition happens (see Section 6.8). (2) IRQ is cleared when RX FIFO drops below trigger level. Fig 17. Receive timing in 68 mode D0 D1 D2 D3 D4 D5 D6 D7 active active 16 baud rate clock 002aac619 td(CS-IRQH)R next data start bit stop bit parity bit start bit td(stop-IRQL) RXA, RXB IRQ(1)(2) CS (read) data bits (0 to 7) 5 data bits 6 data bits 7 data bits |
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