SC16C852LIB datasheet(26/60 Pages) PHILIPS

26 / 60 page

SC16C852L_2

Product data sheet

Rev. 02 — 25 January 2007

26 of 60

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger

levels, and select the DMA mode.

7.3.1 DMA mode

7.3.1.1

Mode 0 (FCR bit 3 = 0)

In this mode, Transmit Ready (TXRDY) will go to a logic 0 whenever the FIFO (THR, if

FIFO is not enabled) is empty. Receive Ready (RXRDY) will go to a logic 0 whenever the

Receive Holding Register (RHR) is loaded with a character.

7.3.1.2

Mode 1 (FCR bit 3 = 1)

In this mode, the Transmit Ready (TXRDY) is set when the transmit FIFO is below the

programmed trigger level. The Receive Ready (RXRDY) is set when the receive FIFO ﬁlls

to the programmed trigger level. However, the FIFO continues to ﬁll regardless of the

programmed level until the FIFO is full. RXRDY remains a logic 0 as long as the FIFO ﬁll

level is above the programmed trigger level.

7.3.2 FIFO mode

Table 12.

FIFO Control Register bits description

Bit

Symbol

Description

7:6

FCR[7:6]

Receive trigger level in 32-byte FIFO mode[1].

These bits are used to set the trigger levels for receive FIFO interrupt and

ﬂow control. The SC16C852L will issue a receive ready interrupt when the

number of characters in the receive FIFO reaches the selected trigger level.

Refer to Table 13.

5:4

FCR[5:4]

Transmit trigger level in 32-byte FIFO mode[2].

These bits are used to set the trigger level for the transmit FIFO interrupt and

ﬂow control. The SC16C852L will issue a transmit empty interrupt when the

number of characters in FIFO drops below the selected trigger level. Refer to

Table 14.

FCR[3]

DMA mode select.

logic 0 = set DMA mode ‘0’ (normal default condition)

logic 1 = set DMA mode ‘1’

Transmit operation in mode ‘0’: When the SC16C852L is in the non-FIFO

mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs

enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no

characters in the transmit FIFO, the TXRDYA/TXRDYB pin will be a logic 0.

Once active, the TXRDYA/TXRDYB pin will go to a logic 1 after the ﬁrst

character is loaded into the transmit holding register.

Receive operation in mode ‘0’: When the SC16C852L is in non-FIFO

mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and there is

at least one character in the receive FIFO, the RXRDYA/RXRDYB pin will be

a logic 0. Once active, the RXRDYA/RXRDYB pin will go to a logic 1 when

there are no more characters in the receiver.

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