SC16C852LIB datasheet(42/60 Pages) PHILIPS

42 / 60 page

SC16C852L_2

Product data sheet

Rev. 02 — 25 January 2007

42 of 60

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

[1]

Applies to external clock, crystal oscillator max 24 MHz.

[2]

Maximum frequency =

[3]

RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.

Table 40.

Dynamic characteristics - Motorola or 68 mode

Tamb = −40 °C to +85 °C; VDD = 1.65 V to 1.95 V; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tWH

pulse width HIGH

tWL

pulse width LOW

tw(clk)

clock pulse width

12.5

fXTAL1

frequency on pin XTAL1

[1][2] --80

MHz

tsu(A)

address setup time

th(A)

address hold time

tsu(RWL-CSL)

set-up time from R/W LOW to CS LOW

tsu(RWH-CSL)

set-up time from R/W HIGH to CS LOW

td(stop-RXRDY)

delay time from stop to RXRDY

[3] --1TRCLK

td(start-TXRDY)

delay time from start to TXRDY

[3] --8TRCLK

tw(CS)

CS pulse width

25 pF load

td(CS)

CS delay time

25 pF load

td(CS-Q)

delay time from CS to data output

25 pF load

tdis(CS-QZ)

disable time from CS to high-impedance

data output

25 pF load

th(CS-RWH)

hold time from CS to R/W HIGH

td(RW)

R/W delay time

tsu(D-CSH)

set-up time from data input to CS HIGH

th(CSH-D)

data input hold time after CS HIGH

td(modem-IRQL)

delay time from modem to IRQ LOW

td(CS-IRQH)R

read delay time from CS to IRQ HIGH

td(stop-IRQL)

delay time from stop to IRQ LOW

[3] --1TRCLK

td(CS-RXRDYH)R

read delay time from CS to RXRDY HIGH

td(CS-TX)W

write delay time from CS to TX

[3] 8TRCLK

24TRCLK s

td(start-IRQL)

delay time from start to IRQ LOW

[3] --1TRCLK

td(CS-IRQH)W

write delay time from CS to IRQ HIGH

td(CS-TXRDYH)W

write delay time from CS to TXRDY HIGH

td(CS-Q)W

write delay time from CS to data output

tw(RESET_N)

pulse width on pin RESET

baud rate divisor

(216

− 1)

wclk

()

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