SC16C852LIB datasheet(9/60 Pages) PHILIPS

9 / 60 page

SC16C852L_2

Product data sheet

Rev. 02 — 25 January 2007

9 of 60

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

[1]

HVQFN package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply ground

for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to

the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be

incorporated in the PCB in the thermal pad region.

TXA

Transmit data A, B. These outputs are associated with individual serial

transmit channel data from the SC16C852L. The TX signal will be a logic 1

during reset, idle (no data), or when the transmitter is disabled. During the local

loopback mode, the TXA/TXB output pin is disabled and TX data is internally

connected to the UART RX input.

TXB

TXRDYA43

Transmit Ready A, B (active LOW). These outputs provide the TX FIFO/THR

status for individual transmit channels (A to B). TXRDY is primarily intended for

monitoring DMA mode 1 transfers for the transmit data FIFOs. An individual

channel’s TXRDYA, TXRDYB buffer ready status is indicated by logic 0, that is,

at lease one location is empty and available in the FIFO or THR. This pin goes

to a logic 1 (DMA mode 1) when there are no more empty locations in the FIFO

or THR. This signal can also be used for single mode transfers (DMA mode 0).

TXRDYB

VDD

Power supply input.

VSS

13[1]

Signal and power ground.

XTAL1

Crystal or external clock input. Functions as a crystal input or as an external

clock input. A crystal can be connected between this pin and XTAL2 to form an

internal oscillator circuit. Alternatively, an external clock can be connected to

this pin to provide custom data rates (see Section 6.9 “Programmable baud rate

generator”). See Figure 6.

XTAL2

Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal

oscillator output or buffered clock output. Should be left open if an external

clock is connected to XTAL1.

LOWPWR

Low Power. When asserted (active HIGH), the device immediately goes into

low power mode. The oscillator is shut-off and some host interface pins are

isolated from the host’s bus to reduce power consumption. The device only

returns to normal mode when the LOWPWR pin is de-asserted. On the

negative edge of a de-asserting LOWPWR signal, the device is automatically

reset and all registers return to their default reset states. This pin has an

internal pull-down resistor, therefore, it can be left unconnected.

16/68

Bus select. Intel or Motorola bus select.

When 16/68 pin is at logic 1 or left unconnected (internally pulled-up) the

device will operate in Intel bus type of interface.

When 16/68 pin is at logic 0, the device will operate in Motorola bus type of

interface.

Table 2.

Pin description …continued

Symbol

Type

Description

LQFP48

HVQFN32

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