SC16C852LIB datasheet(15/60 Pages) PHILIPS

15 / 60 page

SC16C852L_2

Product data sheet

Rev. 02 — 25 January 2007

15 of 60

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

each time the Receive Holding Register (RHR) is read. The actual time-out value is

4 character time, including data information length, start bit, parity bit, and the size of stop

bit, that is, 1

×, 1.5×, or 2× bit times.

6.9 Programmable baud rate generator

The SC16C852L UART contains a programmable rational baud rate generator that takes

any clock input and divides it by a divisor in the range between 1 and (216

− 1). The

SC16C852L offers the capability of dividing the input frequency by rational divisor. The

fractional part of the divisor is controlled by the CLKPRES register in the ‘ﬁrst extra feature

(1)

where:

N is the integer part of the divisor in DLL and DLM registers;

M is the fractional part of the divisor in CLKPRES register;

fXTAL1 is the clock frequency at XTAL1 pin.

Prescaler = 1 when MCR[7] is set to 0.

Prescaler = 4 when MCR[7] is set to 1.

A single baud rate generator is provided for the transmitter and receiver. The

programmable Baud Rate Generator is capable of operating with a frequency of up to

80 MHz. To obtain maximum data rate, it is necessary to use full rail swing on the clock

input. The SC16C852L can be conﬁgured for internal or external clock operation. For

internal clock operation, an industry standard crystal is connected externally between the

XTAL1 and XTAL2 pins (see Figure 6). Alternatively, an external clock can be connected

to the XTAL1 pin (see Figure 7) to clock the internal baud rate generator for standard or

custom rates (see Table 7).

The generator divides the input 16

× clock by any divisor from 1 to (216 − 1). The

SC16C852L divides the basic external clock by 16. The baud rate is conﬁgured via the

CLKPRES, DLL and DLM internal register functions. Customized baud rates can be

achieved by selecting the proper divisor values for the MSB and LSB sections of the baud

rate generator.

Fig 5.

Prescalers and baud rate generator block diagram

baud rate

XTAL1

MCR 7

[]

------





--------------------------------------------------------------------

002aac645

OSCILLATOR

XTAL1

XTAL2

DIVIDE-BY-1

DIVIDE-BY-4

CLKPRES

[3:0]

BAUD RATE

GENERATOR

(DLL, DLM)

transmitter and

receiver clock

MCR[7] = 0

MCR[7] = 1

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