SC16C852LIB datasheet(7/60 Pages) PHILIPS

7 / 60 page

SC16C852L_2

Product data sheet

Rev. 02 — 25 January 2007

7 of 60

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

5.2 Pin description

Table 2.

Pin description

Symbol

Type

Description

LQFP48

HVQFN32

Address 0 select bit. Internal register address selection.

Address 1 select bit. Internal register address selection.

Address 2 select bit. Internal register address selection.

CDA40

Carrier Detect (active LOW). These inputs are associated with individual

UART channels A through B. A logic 0 on this pin indicates that a carrier has

been detected by the modem for that channel.

CDB

CSA/CS

When 16/68 pin is at logic 1 (or unconnected), this input is chip select for

channel A.

When 16/68 pin is at logic 0, this input becomes the chip select for both

channels (Motorola mode).

CSB/A3

When 16/68 pin is at logic 1 (or unconnected), this input is chip select for

channel B.

When 16/68 pin is at logic 0, this input becomes the address line A3 which is

used for channel selection; a logic 0 selects channel A and a logic 1 selects

channel B.

CTSA

Clear to Send (active LOW). These inputs are associated with individual

UART channels, A through B. A logic 0 on the CTSx pin indicates the modem or

data set is ready to accept transmit data from the SC16C852L. Status can be

tested by reading MSR[4].

CTSB

DSRA

Data Set Ready (active LOW). These inputs are associated with individual

UART channels, A through B. A logic 0 on this pin indicates the modem or data

set is powered-on and is ready for data exchange with the UART. Status can be

tested by reading MSR[5].

DSRB

DTRA

Data Terminal Ready (active LOW). These outputs are associated with

individual UART channels, A through B. A logic 0 on this pin indicates that the

SC16C852L is powered-on and ready. This pin can be controlled via the

modem control register. Writing a logic 1 to MCR[0] will set the DTR output to

logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to

MCR[0], or after a reset.

DTRB

I/O

Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for

transferring information to or from the controlling CPU. D0 is the least

signiﬁcant bit and the ﬁrst data bit in a transmit or receive serial data stream.

I/O

INTA

(IRQ)

When 16/68 pin is at logic 1 or unconnected, this output becomes channel A

interrupt output. The output state is deﬁned by the user through the software

setting of MCR[3]. INTA is set to the active mode and OP2A output to a logic 0

when MCR[3] is set to a logic 1. INTA is set to the 3-state mode and OP2A is

set to a logic 1 when MCR[3] is set to a logic 0.

When 16/68 pin is at logic 0, this output becomes device interrupt output

(active LOW, open-drain). An external pull-up resistor to VDD is required.

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