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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC16C852LIB датащи(PDF) 16 Page - NXP Semiconductors |
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SC16C852LIB датащи(HTML) 16 Page - NXP Semiconductors |
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16 / 60 page  SC16C852L_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 25 January 2007 16 of 60 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder Programming the baud rate generator registers CLKPRES, DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired final baud rate. The example in Table 7 shows the selectable baud rate table available when using a 1.8432 MHz external clock input when MCR[7] = 0, and CLKPRES = 0x00. Fig 6. Crystal oscillator connection If fXTAL1 frequency is greater than 50 MHz, then a DC blocking capacitor is required. XTAL2 pin should be left unconnected when an external clock is used. Fig 7. External clock connection Table 7. Baud rate generator programming table using a 1.8432 MHz clock when MCR[7] = 0 and CLKPRES[3:0] = 0 Output baud rate (bit/s) Output 16 × clock divisor (decimal) Output 16 × clock divisor (hexadecimal) DLM program value (hexadecimal) DLL program value (hexadecimal) 50 2304 900 09 00 75 1536 600 06 00 110 1047 417 04 17 150 768 300 03 00 300 384 180 01 80 600 192 C0 00 C0 1.2 k 96 60 00 60 2.4 k 48 30 00 30 3.6 k 32 20 00 20 4.8 k 24 18 00 18 7.2 k 16 10 00 10 9.6 k 12 0C 00 0C 19.2 k 6 06 00 06 002aaa870 C2 47 pF XTAL1 XTAL2 X1 1.8432 MHz C1 22 pF C2 33 pF XTAL1 XTAL2 1.5 k Ω X1 1.8432 MHz C1 22 pF 002aac630 XTAL1 XTAL2 100 pF fXTAL1 |
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