SC16C852LIB datasheet(20/60 Pages) PHILIPS

20 / 60 page

SC16C852L_2

Product data sheet

Rev. 02 — 25 January 2007

20 of 60

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

6.14 RS-485 features

6.14.1 Auto RS-485 RTS control

Normally the RTSA/RTSB pin is controlled by MCR bit 1, or if hardware ﬂow control is

enabled, the logic state of the RTSx pin is controlled by the hardware ﬂow control circuitry.

AFCR2 register bit 4 will take the precedence over the other two modes; once this bit is

set, the transmitter will control the state of the RTSx pin. The transmitter automatically

asserts the RTSx pin (logic 0) once the host writes data to the transmit FIFO, and

de-asserts RTSx pin (logic 1) once the last bit of the data has been transmitted.

To use the auto RS-485 RTS mode the software would have to disable the hardware

ﬂow control function.

6.14.2 RS-485 RTS inversion

AFCR2[5] reverses the polarity of the RTSx pin if the UART is in auto RS-485 RTS mode.

When the transmitter has data to be sent it will de-asserts the RTSx pin (logic 1), and

when the last bit of the data has been sent out the transmitter asserts the RTSx pin

(logic 0).

6.14.3 Auto 9-bit mode (RS-485)

AFCR2[0] is used to enable the 9-bit mode (Multi-drop or RS-485 mode). In this mode of

operation, a ‘master’ station transmits an address character followed by data characters

for the addressed ‘slave’ stations. The slave stations examine the received data and

interrupt the controller if the received character is an address character (parity bit = 1).

To use the automatic 9-bit mode, the software would have to disable the hardware and

software ﬂow control functions.

6.14.3.1

Normal Multi-drop mode

The 9-bit Mode in AFCR2[0] is enabled, but not Special Character Detect (EFR[5]). The

receiver is set to Force Parity 0 (LCR[5:3] = 111) in order to detect address bytes.

With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an

address byte is received (parity bit = 1). This address byte will cause the UART to set the

parity error. The UART will generate a line status interrupt (IER bit 2 must be set to ‘1’ at

this time), and at the same time puts this address byte in the RX FIFO. After the controller

examines the byte it must make a decision whether or not to enable the receiver; it should

enable the receiver if the address byte addresses its ID address, and must not enable the

receiver if the address byte does not address its ID address.

If the controller enables the receiver, the receiver will receive the subsequent data until

being disabled by the controller after the controller has received a complete message from

the ‘master’ station. If the controller does not disable the receiver after receiving a

message from the ‘master’ station, the receiver will generate a parity error upon receiving

another address byte. The controller then determines if the address byte addresses its ID

address, if it is not, the controller then can disable the receiver. If the address byte

addresses the ‘slave’ ID address, the controller takes no further action, and the receiver

will receive the subsequent data.

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