SC16C852LIB datasheet(25/60 Pages) PHILIPS

25 / 60 page

SC16C852L_2

Product data sheet

Rev. 02 — 25 January 2007

25 of 60

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation

When the receive FIFO is enabled (FCR[0] = logic 1), and receive interrupts

(IER[0] = logic 1) are enabled, the receive interrupts and register status will reﬂect the

following:

• The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU

when the receive FIFO has reached the programmed trigger level. It will be cleared

when the receive FIFO drops below the programmed trigger level.

• Receive FIFO status will also be reﬂected in the user accessible ISR register when

the receive FIFO trigger level is reached. Both the ISR register receive status bit and

the interrupt will be cleared when the FIFO drops below the trigger level.

• The receive data ready bit (LSR[0]) is set as soon as a character is transferred from

the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty.

• When the Transmit FIFO and interrupts are enabled, an interrupt is generated when

the transmit FIFO is empty due to the unloading of the data by the TSR and UART for

transmission via the transmission media. The interrupt is cleared either by reading the

ISR, or by loading the THR with new data characters.

7.2.2 IER versus Receive/Transmit FIFO polled mode operation

When FCR[0] = logic 1, setting IER[3:0] puts the SC16C852L in the FIFO polled mode of

operation. In this mode, interrupts are not generated and the user must poll the LSR

bits in the LSR either or both can be used in the polled mode by selecting respective

transmit or receive control bit(s).

• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

• LSR[4:1] will provide the type of receive errors, or a receive break, if encountered.

• LSR[5] will indicate when the transmit FIFO is empty.

• LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.

• LSR[7] will show if any FIFO data errors occurred.

IER[1]

Transmit Holding Register interrupt. In the non-FIFO mode, this interrupt will be

issued whenever the THR is empty, and is associated with LSR[5]. In the FIFO

modes, this interrupt will be issued whenever the FIFO is empty.

logic 0 = disable the Transmit Holding Register Empty (TXRDY) interrupt

(normal default condition)

logic 1 = enable the TXRDY (ISR level 3) interrupt

IER[0]

Receive Holding Register interrupt. In the non-FIFO mode, this interrupt will be

issued when the RHR has data, or is cleared when the RHR is empty. In the FIFO

mode, this interrupt will be issued when the FIFO has reached the programmed

trigger level or is cleared when the FIFO drops below the trigger level.

logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt (normal

default condition)

logic 1 = enable the RXRDY (ISR level 2) interrupt

Table 11.

Interrupt Enable Register bits description …continued

Bit

Symbol

Description

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