SC16C852LIB datasheet(10/60 Pages) PHILIPS

10 / 60 page

SC16C852L_2

Product data sheet

Rev. 02 — 25 January 2007

10 of 60

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

Functional description

The SC16C852L provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for converting the serial data stream into

parallel data that is required with digital data systems. Synchronization for the serial data

stream is accomplished by adding start and stop bits to the transmit data to form a data

character (character orientated protocol). Data integrity is ensured by attaching a parity bit

to the data character. The parity bit is checked by the receiver for any transmission bit

errors. The electronic circuitry to provide all these functions is fairly complex, especially

when manufactured on a single integrated silicon chip. The SC16C852L represents such

an integration with greatly enhanced features. The SC16C852L is fabricated with an

advanced CMOS process.

The SC16C852L is an upward solution to the SC16C652B that provides a dual UART

capability with 128 bytes of transmit and receive FIFO memory, instead of 32 bytes for the

16C652 and 16 bytes in the 16C2550. The SC16C852L is designed to work with high

speed modems and shared network environments that require fast data processing time.

Increased performance is realized in the SC16C852L by the transmit and receive FIFOs.

This allows the external processor to handle more networking tasks within a given time. In

addition, the four selectable receive and transmit FIFO trigger interrupt levels are provided

in 16C652 mode, or 128 programmable levels are provided in the extended mode for

maximum data throughput performance especially when operating in a multi-channel

environment (see Section 6.2 “Extended mode (128-byte FIFO)”). The FIFO memory

greatly reduces the bandwidth requirement of the external controlling CPU and increases

performance. A low power pin (LOWPWR) is provided to further reduce power

consumption by isolating the host bus interface.

The SC16C852L is capable of operation up to 5 Mbit/s with an external 80 MHz clock.

With a crystal, the SC16C852L is capable of operation up to 1.5 Mbit/s.

The rich feature set of the SC16C852L is available through internal registers. These

features are: selectable and programmable receive and transmit FIFO trigger levels,

selectable TX and RX baud rates, and modem interface controls, and are all standard

features. Following a power-on reset, an external reset, or a software reset, the

SC16C852L is software compatible with the previous generation, SC16C2550,

SC16C652B, and ST16C2450.

6.1 UART A-B functions

The UART provides the user with the capability to bidirectionally transfer information

between an external CPU, the SC16C852L package, and an external serial device. A

logic 0 (LOW) on chip select pins CSA and/or CSB allows the user to conﬁgure, send

data, and/or receive data via UART channels A, B. Individual channel select functions are

shown in Table 3 and Table 4.

Table 3.

Serial port selection (Intel interface)

H = HIGH; L = LOW.

Chip Select

Function

CSA = H, CSB = H

none

CSA = L

UART channel A

CSB = L

UART channel B

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