SC16C852LIB datasheet(13/60 Pages) PHILIPS

13 / 60 page

SC16C852L_2

Product data sheet

Rev. 02 — 25 January 2007

13 of 60

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

6.5 Hardware ﬂow control

When automatic hardware ﬂow control is enabled, the SC16C852L monitors the

CTSA/CTSB pin for a remote buffer overﬂow indication and controls the RTSA/RTSB pin

for local buffer overﬂows. Automatic hardware ﬂow control is selected by setting EFR[6]

(RTS) and EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1

indicating a ﬂow control request, ISR[5] will be set to a logic 1 (if enabled via IER[7:6]),

and the SC16C852L will suspend TX transmissions as soon as the stop bit of the

character in process is shifted out. Transmission is resumed after the CTSx input returns

to a logic 0, indicating more data may be sent.

When AFCR1[2] is set to logic 1 then the function of CTSA/CTSB pin is mapped to the

DSRA/DSRB pin, and the function of RTSA/RTSB is mapped to DTRA/DTRB pin. DSRx

and DTRx pins will behave as described above for CTS and RTS.

With the automatic hardware ﬂow control function enabled, an interrupt is generated when

the receive FIFO reaches the programmed trigger level. The RTSx (or DTRx) pin will not

be forced to a logic 1 (RTS off), until the receive FIFO reaches the next trigger level.

However, the RTSx (or DTRx) pin will return to a logic 0 after the receive buffer (FIFO) is

unloaded to the next trigger level below the programmed trigger level. Under the above

described conditions, the SC16C852L will continue to accept data until the receive FIFO

is full.

When the TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL in the ‘ﬁrst extra feature

FCR[7:4]; see Table 6.

When the TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the ‘ﬁrst extra feature

trigger levels are set by FLWCNTH and FLWCNTL. The content in FLWCNTH determines

how many bytes are in the receive FIFO before RTS (or DTR) is de-asserted or Xoff is

sent. The content in FLWCNTL determines how many bytes are in the receive FIFO

before RTS (or DTR) is asserted, or Xon is sent.

In 128-byte FIFO mode, hardware and software ﬂow control trigger levels can be set to

any value between 1 and 128 in granularity of 1. The value of FLWCNTH should always

be greater than FLWCNTL. The UART does not check for this condition automatically, and

if this condition is not met, spurious operation of the device might occur. When using

FLWCNTH and FLWCNTL, these registers must be initialized to proper values before

hardware or software ﬂow control is enabled via the EFR register.

6.6 Software ﬂow control

When software ﬂow control is enabled, the SC16C852L compares one or two sequentially

received data characters with the programmed Xon or Xoff character value(s). If the

received character(s) match the programmed Xoff values, the SC16C852L will halt

transmission (TX) as soon as the current character(s) has completed transmission. When

a match occurs, ISR bit 4 will be set (if enabled via IER[5]) and the interrupt output pin (if

receive interrupt is enabled) will be activated. Following a suspension due to a match of

the Xoff characters’ values, the SC16C852L will monitor the receive data stream for a

match to the Xon1/Xon2 character value(s). If a match is found, the SC16C852L will

resume operation and clear the ﬂags (ISR[4]).

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