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SC16C852LIB датащи(PDF) 33 Page - NXP Semiconductors |
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SC16C852LIB датащи(HTML) 33 Page - NXP Semiconductors |
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33 / 60 page ![]() SC16C852L_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 25 January 2007 33 of 60 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder 7.9 Extra Feature Control Register (EFCR) This is a write-only register, and it allows the software access to these registers: first extra feature register set, second extra feature register set, Transmit FIFO Level Counter (TXLVLCNT), and Receive FIFO Level Counter (RXLVLCNT). Remark: EFCR[2:1] has higher priority than EFCR[0]. TXLVLCNT and RXLVLCNT can only be accessed if EFCR[2:1] are zeroes. 7.10 Scratchpad Register (SPR) The SC16C852L provides a temporary data register to store 8 bits of user information. 7.11 Division Latch (DLL and DLM) These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock in the baud rate generator. DLM, stores the most significant part of the divisor. DLL stores the least significant part of the division. 7.12 Transmit FIFO Level Count (TXLVLCNT) This register is a read-only register. It reports the number of characters available in the transmit FIFO. 7.13 Receive FIFO Level Count (RXLVLCNT) This register is a read-only register. It reports the fill level of the receive FIFO (the number of characters in the RX FIFO). Table 24. Extra Feature Control Register bits description Bit Symbol Description 7:3 EFCR[7:3] reserved 2:1 EFCR[2:1] Enable Extra Feature Control bits 00 = General register set is accessible 01 = First extra feature register set is accessible 10 = Second extra feature register set is accessible 11 = reserved 0 EFCR[0] Enable TXLVLCNT and RXLVLCNT access 0 = TXLVLCNT and RXLVLCNT are disabled 1 = TXLVLCNT and RXLVLCNT are enabled and can be read. |
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