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SC16C852LIB датащи(PDF) 49 Page - NXP Semiconductors |
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SC16C852LIB датащи(HTML) 49 Page - NXP Semiconductors |
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49 / 60 page ![]() SC16C852L_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 25 January 2007 49 of 60 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder (1) INT is active when TX FIFO is empty or TX FIFO drops below trigger level. (2) INT is cleared when ISR is read or TX FIFO fills up to trigger level. Fig 22. Transmit timing in 16 mode active transmitter ready active 16 baud rate clock 002aac616 td(IOW-INTL) INT(1)(2) IOW active D0 D1 D2 D3 D4 D5 D6 D7 TXA, TXB 5 data bits 6 data bits 7 data bits stop bit parity bit start bit data bits (0 to 7) next data start bit td(start-INT) td(IOW-TX) (1) IRQ is active when TX FIFO is empty or TX FIFO drops below trigger level. (2) IRQ is cleared when ISR is read or TX FIFO fills up to trigger level. Fig 23. Transmit timing in 68 mode D0 D1 D2 D3 D4 D5 D6 D7 active TX ready active 16 baud rate clock 002aac622 td(CS-IRQH)W start bit td(start-IRQL) TXA, TXB IRQ(1)(2) CS (write) data bits (0 to 7) active td(CS-TX)W 5 data bits 6 data bits 7 data bits parity bit stop bit next data start bit |
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