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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMPR4955AF датащи(PDF) 158 Page - Toshiba Semiconductor |
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TMPR4955AF датащи(HTML) 158 Page - Toshiba Semiconductor |
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158 / 168 page  Chapter 10 Electrical Characteristics 10-2 10.1.3 DC Characteristics TC = 0°C to 70°C, VccInt = 1.5 V ± 0.1 V, VccIO = 3.3 V ± 0.2 V Parameter Symbol Conditions Min Typ. Max Units Output High Voltage VOH VccIO = 3.3 V, Vss = 0 V IOH = −4 mA 2.4 V Output Low Voltage VOL VccIO = 3.3 V, Vss = 0 V IOL = 4 mA 0.4 V Input High Voltage (*2) VIH 2.0 VccIO + 0.3 V Input Low Voltage (*1,2) VIL -0.5 (*1) 0.8 V Operating Current (Internal) ICCInt VccIO = 3.5 V, VccInt = 1.6 V, MasterClock = 100 MHz PClock = 200 MHz 350 550 mA Operating Current (I/O) ICCIO VccIO = 3.5 V, VccInt = 1.6 V, MasterClock = 100 MHz PClock = 200 MHz 50 60 mA Input Leakage ILI Except (*3) port ±10 µA Pull-up (*3) Rinu 30 50 100 K Ω Pull-down (*4) Rind 30 50 100 K Ω Output Leakage ILO ±20 µA Input Capacitance CIN 10 pF Output Capacitance COUT 10 pF (*1) VIL Min = − 1.5 V for pulse width less than 10 ns. (*2) Except for MasterClock input (*3) Applies to Int(5:0)*, NMI*, RESET*, JTMS, JTCK, JTDI, TPC1 inputs (*4) Applies to TRST*, RdRdy*, TPC3, TPC2 inputs 10.1.4 AC Characteristics 10.1.4.1 Clock Timing TC = 0°C to 70°C, VccInt = 1.5 V ± 0.1 V, VccIO = 3.3 V ± 0.2 V Parameter Symbol Conditions Min Max Units MasterClock High tMCH Transition 5 ns 3.0 ns MasterClock Low tMCL Transition 5 ns 3.0 ns MasterClock Frequency (*1) fMCK 20 100 MHz Internal Operation Frequency fPCK 50 200 MHz MasterClock Period tMCP 10 50 ns MasterClock Rise Time tMCR 2.0 ns MasterClock Fall Time tMCF 2.0 ns (*1) Operation of TMPR4955AF is only guaranteed with the Phase Lock Loop enabled. (*2) All output timings assume a 25 pF capacitive load. Output timings should be derated where appropriate. 10.1.4.2 System Interface TC = 0°C to 70°C, VccInt = 1.5 V ± 0.1 V, VccIO = 3.3 V ± 0.2 V, BufSel = 100% Parameter Symbol Min Max Units Data Output (*1, 2, 3) tDO 1.0 6.5 ns Data Setup (*3) tDS 3.5 ns Data Hold (*3) tDH 1.0 ns (*1) Timings are measured from 1.5 V of the MasterClock to 1.5 V of signal. (*2) Capacitive load for all output timings is 25 pF. (*3) Data Output, Data Setup and Data Hold apply to all logic signals driven out of or driven into the TMPR4955AF on the system interface. Clocks are specified separately. |
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